Charge Trap Flash Memory Nanodot Structure for Low Voltage Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Charge trap flash memory devices face challenges in maintaining charge storage capacity and preventing charge loss due to low electron trap site density and high operating voltages in existing SONOS and MONOS structures, which also suffer from insufficient charge retention and high disturbance characteristics.
Innovation Solution
A charge trap flash memory device is designed with a structure that includes a tunnel insulating layer, a charge trap layer comprising multiple trap layers with nanodots and an intermediate blocking layer, where the nanodots have a lower band gap energy and the intermediate blocking layer has a higher band gap energy, enhancing charge storage capacity and retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon nitride layer is used as a charge trap layer in SONOS memory, then charge storage is enabled, but the dielectric constant is low and electron trap site density is insufficient, resulting in high operating voltage and low program speed
Solution Approach 1:
The patent employs a composite charge trap layer structure combining silicon nitride (high electron trap site density) with high-k dielectric materials (high dielectric constant). This composite approach simultaneously achieves sufficient charge storage capacity and fast program speed by leveraging the complementary strengths of different materials, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent modifies the physical and chemical parameters of the charge trap layer by adjusting material composition, layer thickness, and trap site density. By optimizing these parameters, the device achieves both high charge storage capacity and low operating voltage, thereby improving both reliability and program speed.
2Quantity of substance
If memory cell size is reduced to increase memory capacity, then storage density improves, but charge retention characteristics deteriorate and disturbance between cells increases
Solution Approach 1:
The patent applies local quality enhancement by creating a charge trap layer with spatially varying properties - specifically, a gradient in trap site density and dielectric constant across the layer thickness. This local optimization ensures sufficient charge retention even in miniaturized memory cells, maintaining reliability while enabling higher capacity.
Solution Approach 2:
The patent implements a nested multi-layer charge trap structure where different functional layers are embedded within each other. The inner layer provides charge storage while outer layers provide retention and isolation, allowing small memory cells to maintain excellent charge retention characteristics through hierarchical functional organization.
3Use of energy by moving object
If operating voltage is reduced to improve device safety and reduce power consumption, then energy efficiency improves, but charge storage capacity and program speed deteriorate
Solution Approach 1:
The patent changes the dielectric parameters of the charge trap layer by incorporating high-k materials, which increase the dielectric constant and reduce the tunneling barrier height. This allows charge injection and storage at lower voltages, simultaneously improving power efficiency and maintaining charge storage capacity.
Solution Approach 2:
The composite charge trap layer combining high-k dielectric materials with silicon nitride creates a structure that achieves both low operating voltage and high charge storage capacity. The high-k material reduces the voltage required for charge tunneling while the silicon nitride provides abundant trap sites, resolving the contradiction between energy efficiency and storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure improves charge storage capacity, reduces charge loss, and achieves lower operating voltages, while maintaining high reliability and endurance, with improved program and erase speeds.
Implementation Method 1
the nanodots including a second material having a second band gap energy level that is lower than the first band gap energy level
Implementation Method 2
an intermediate blocking layer formed between at least two of the plurality of trap layers, the intermediate blocking layer including a third material having a third band gap energy level that is higher than the first band gap energy level
Implementation Method 3
A first silicon oxide (SiO2) layer is formed on a semiconductor substrate between a source region and a drain region, and contacts the source region and the drain region. Also, the first silicon oxide layer is a tunnel insulating layer for tunneling charges.
Data Source
AI summary
The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.