Vertical Nanowire Transistor Channel Patterning via Directed Self-Assembly
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Solution Overview
Problem
Current techniques fail to accurately pattern vertical nanowire transistors with features below 15 nm in diameter and pitches below 30 nm, lacking sufficient critical dimension uniformity and circularity, which is beyond the capability of existing lithographic methods and requires expensive toolsets.
Innovation Solution
The use of directed self-assembly (DSA) materials, such as di-block copolymers, to pattern channel regions of vertical nanowire transistors through a single lithographic operation, allowing for self-aligned feature formation with dimensions smaller than what conventional lithography can achieve, by segregating polymers within guide openings to define semiconductor channel regions and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic methods are used to pattern nanowire features, then manufacturing process is simpler, but feature dimensions cannot achieve 15 nm or less with sufficient critical dimension uniformity and circularity
Solution Approach 1:
The patent segments the patterning process into two distinct stages: first forming guide openings at a relaxed pitch using conventional lithography, then using directed self-assembly to sub-segment these guide openings into smaller nanowire features. This segmentation allows each stage to optimize for its specific function, achieving sub-lithographic dimensions while maintaining manufacturing feasibility.
Solution Approach 2:
The patent introduces guide openings as an intermediary structure that mediates between the conventional lithographic process and the final nanowire pattern. These guide openings serve as templates that direct the self-assembly process, enabling the formation of smaller features than directly printable with conventional lithography while maintaining alignment and uniformity.
2Manufacturing precision
If features are printed larger and then shrunk, then manufacturing is easier, but desired pitches cannot be achieved
Solution Approach 1:
The patent transitions from direct 2D lithographic patterning to a 3D self-assembly process where block copolymers spontaneously organize within guide openings. This dimensional transition allows the system to achieve pitch reduction through self-organized phase separation rather than mechanical shrinking, maintaining manufacturing simplicity while achieving superior pitch control.
Solution Approach 2:
The patent employs self-service by utilizing the inherent self-organizing properties of block copolymers to automatically form the desired nanowire patterns without requiring additional lithographic steps or complex processing. The block copolymers self-assemble into periodic structures that define the final feature pitch, eliminating the need for manual pattern shrinking operations.
3Manufacturing precision
If advanced lithographic toolsets are used to achieve sub-15 nm features, then feature dimensions improve, but manufacturing cost increases
Solution Approach 1:
The patent performs preliminary action by pre-forming guide openings at a larger, more economically manufacturable pitch using conventional lithography. This preliminary structure then guides the subsequent self-assembly process to achieve the final sub-lithographic features, avoiding the need for expensive advanced lithographic tools while maintaining high precision.
Solution Approach 2:
The patent changes the physical and chemical parameters of the system by introducing block copolymers with specific molecular weights, compositions, and architectures that self-assemble at desired length scales. By controlling parameters such as block copolymer composition, guide opening dimensions, and annealing conditions, the system achieves sub-lithographic feature sizes using cost-effective conventional lithography combined with self-assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of vertical nanowire transistors with sub-lithographic dimensions, achieving precise alignment and reduced feature pitch, thereby improving transistor density and performance at a lower manufacturing cost.
Implementation Method 1
The use of directed self-assembly (DSA) materials, such as di-block copolymers, to pattern channel regions of vertical nanowire transistors through a single lithographic operation, allowing for self-aligned feature formation
Data Source
AI summary
Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.