Nanowire Transistor Surrounding Gate Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional transistor structures face challenges in scaling down device size while maintaining low power consumption and high performance, particularly due to issues with sub-threshold leakage current and carrier mobility, especially in deep sub-micron regions where junction depths and channel lengths are difficult to manage effectively.
Innovation Solution
The development of nanowire transistors with a surrounding gate structure, where silicon nanorods are recrystallized using solid phase epitaxial growth and integrated with a wraparound gate, allowing for dimensions smaller than lithographic limits and improved control over the transistor channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional MOSFET scaling is continued to deep sub-micron region, then device size is reduced, but sub-threshold leakage current increases and carrier mobility decreases
Solution Approach 1:
The patent transitions from conventional planar 2D channel structures to three-dimensional nanowire channels with surrounding gates. This dimensional change enables the gate to control the channel from all directions (360-degree wraparound), providing superior electrostatic control and reducing sub-threshold leakage current while maintaining scaled device dimensions.
Solution Approach 2:
The patent employs composite material structures including silicon nanowires embedded in silicon oxide, with surrounding gates formed from conductive materials. This composite approach enables precise control of electrical properties while maintaining mechanical stability and reducing leakage current through material interface engineering.
2Volume of moving object
If conventional MOSFET scaling is continued to deep sub-micron region, then device size is reduced, but carrier mobility decreases due to high doping requirements
Solution Approach 1:
The three-dimensional nanowire channel structure with surrounding gate provides enhanced electrostatic control that suppresses short-channel effects without requiring extremely high channel doping. This dimensional transition allows carriers to move more freely while maintaining effective channel control, thereby preserving carrier mobility at scaled dimensions.
Solution Approach 2:
The patent changes the fundamental geometric parameters of the transistor structure from planar to cylindrical nanowire configuration. This parameter change enables effective channel control through the surrounding gate's electrostatic field, reducing the need for high doping levels and thereby maintaining higher carrier mobility.
3Length of moving object
If junction depths are reduced to maintain scaling, then channel length can be shortened, but junction formation becomes difficult by conventional techniques
Solution Approach 1:
The patent adopts vertical nanowire channels growing from the substrate surface, enabling junction formation through vertical epitaxial growth rather than horizontal implantation. This dimensional change allows precise control of junction depths at ultra-shallow levels (few hundred Angstroms) that are difficult to achieve with conventional planar implantation and diffusion techniques.
Solution Approach 2:
The patent replaces conventional mechanical implantation processes with epitaxial growth methods for forming ultra-shallow junctions. This substitution enables precise control of junction depth and profile at dimensions below what is achievable with traditional ion implantation, facilitating short channel length implementation.
4Reliability
If extremely high channel doping levels are used to suppress short-channel effects, then short-channel effects are reduced, but leakage increases and carrier mobility decreases
Solution Approach 1:
The surrounding gate structure provides 360-degree electrostatic control of the nanowire channel, effectively suppressing short-channel effects through enhanced gate control rather than relying on high doping. This dimensional change in gate configuration allows low-doping operation while maintaining reliability, thereby reducing leakage current.
Solution Approach 2:
The patent changes the controlling parameter for short-channel effect suppression from channel doping concentration to gate electrostatic field strength. This parameter change enables effective suppression of short-channel effects at low doping levels, preventing the increase in leakage and decrease in carrier mobility that would otherwise occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces sub-threshold leakage current and enhances carrier mobility, addressing the limitations of conventional transistors by enabling more efficient device scaling and performance in nanowire transistors with improved gate control.
Implementation Method 1
a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth
Data Source
AI summary
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.