Vertical FETs with Unshielded Organic Semiconductor Layers
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Solution Overview
Problem
Organic molecule-based field effect transistors (FETs) face limitations in high performance due to low charge carrier mobility, requiring higher power consumption and being unsuitable for high-speed applications, primarily due to weak intermolecular interactions and poor crystallinity, which is challenging to overcome, especially in fabricating short channel lengths for mass production.
Innovation Solution
A vertical FET design is implemented with a dielectric layer sandwiched between a gate electrode and a first electrode layer, using dilute percolating carbon nanotube or semiconducting nanowire films as electrodes, and an organic semiconductor layer that extends beyond the electrode area for direct contact with the dielectric, allowing for nanometer-scale control of channel length and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planar organic FET structure is used, then fabrication is simpler, but channel length control precision is insufficient for short channel lengths
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional vertical structure. The vertical FET architecture enables precise control of channel length through vertical stacking of layers (gate electrode, dielectric layer, organic semiconductor layer, source/drain electrodes) rather than relying on lateral lithographic patterning, achieving nanometer-scale channel length control.
Solution Approach 2:
The device is segmented into distinct functional layers stacked vertically: gate electrode layer, dielectric layer, organic semiconductor active layer, and source/drain electrode layers. This segmentation allows independent optimization and precise control of each layer's thickness and properties, particularly enabling accurate channel length definition through dielectric layer thickness control.
2Ease of manufacture
If organic FETs are used, then cost is reduced and flexibility is improved, but charge carrier mobility is low
Solution Approach 1:
The patent optimizes critical parameters including dielectric layer thickness (5-50 nm), organic semiconductor layer thickness (10-100 nm), and vertical electrode positioning to enhance electric field distribution and carrier transport. These parameter optimizations improve charge carrier mobility while preserving the low-cost, flexible manufacturing advantages of organic materials.
Solution Approach 2:
The device employs composite material architecture combining organic semiconductor layers with inorganic dielectric materials and metal electrodes. This composite structure leverages the advantages of each material type: organic semiconductors provide flexibility and low-cost fabrication, while inorganic dielectrics provide precise thickness control and appropriate electrical properties for effective gate control.
3Power
If larger source-drain voltage is applied to overcome low mobility, then current drive capability is improved, but power consumption increases
Solution Approach 1:
The vertical structure enables optimization of the electric field distribution through controlled dielectric thickness and electrode positioning. This enhances the effectiveness of applied gate voltage, improving carrier mobility and current drive capability without requiring proportionally higher power consumption, thereby resolving the trade-off between drive capability and energy efficiency.
Data Source
AI summary
A vertical field effect transistor (FET) comprises a gate electrode and a first electrode layer having a dielectric layer interposed between these electrodes and a semiconducting active layer electrically coupled to the first electrode. The active layer and the dielectric layer sandwich at least a portion of the first electrode where at least one portion of the active layer is unshielded by the first electrode such that the unshielded portion is in direct physical contact with the dielectric layer. A second electrode layer is electrically coupled to the active layer where the second electrode is disposed on at least a portion of the unshielded portion of the active layer such that the second electrode can form electrostatic fields with the gate electrode upon biasing in unscreened regions near the first electrode.