SRAM Cell Inner Spacer Thickness Tuning
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability and multifunctionality due to complex structures and integration demands, particularly in optimizing the electrical characteristics of SRAM cells within these devices.
Innovation Solution
The semiconductor device incorporates a SRAM cell structure with pass-gate and pull-down transistors featuring active fins, channel layers, gate electrodes, source/drain regions, and inner spacers with varying thicknesses and heights, allowing for fine-tuning of threshold voltages and current flow by adjusting the gate lengths of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM cell structures are used, then device integration is achieved, but electrical characteristics such as threshold voltage control and current flow optimization are insufficient
Solution Approach 1:
The patent applies local quality by differentiating the inner spacer structures between pass-gate transistors and pull-down transistors. Specifically, the pass-gate transistor has inner spacers with a first thickness while the pull-down transistor has inner spacers with a second thickness (different from the first). This localized structural differentiation enables independent optimization of threshold voltages and current flow for each transistor type within the SRAM cell, improving electrical characteristics without requiring complete structural redesign.
Solution Approach 2:
The invention segments the inner spacer structures into distinct components for different transistor types within the SRAM cell. By dividing the spacer system into pass-gate inner spacers and pull-down inner spacers with different dimensions, the patent enables independent control and optimization of electrical parameters for each transistor, resolving the contradiction between achieving good electrical characteristics and maintaining structural simplicity.
2Reliability
If inner spacers with uniform thickness are used, then manufacturing is simplified, but threshold voltage tuning and current flow control are limited
Solution Approach 1:
The patent implements local quality by assigning different thickness specifications to inner spacers based on their functional location. The pass-gate transistor inner spacers have a first thickness optimized for pass-gate operation, while pull-down transistor inner spacers have a second thickness optimized for pull-down operation. This localized differentiation provides precise threshold voltage control and current flow management.
Solution Approach 2:
The invention applies parameter changes by varying the inner spacer thickness parameter across different transistor types. By changing the thickness parameter from a uniform value to differentiated values (first thickness for pass-gate, second thickness for pull-down), the patent achieves fine-tuned electrical characteristics while maintaining a relatively simple fabrication process that only requires pattern differentiation.
Data Source
AI summary
A semiconductor device includes a substrate, a SRAM cell including a pass-gate transistor, a pull-down transistor, and a pull-up transistor on substrate. The SRAM cell includes an active fin extending in a first direction, the pass-gate transistor and the pull-down transistor are disposed adjacent to each other on the active fin in the first direction, the pass-gate transistor includes first channel layers, a first gate electrode, first source/drain regions, and first inner spacers, the pull-down transistor includes second channel layers, a second gate electrode, second source/drain regions, and second inner spacers, and one of the first inner spacers and one of the second inner spacers are disposed on the same height level and have different thicknesses in the first direction.