Nanowire Phase Change Memory Device for High Density Low Power Storage
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Solution Overview
Problem
Current non-volatile memory technologies, such as MRAM, FLASH, and FeRAM, fail to achieve ultra-high storage densities and low power consumption, limiting their competitiveness with volatile DRAM and disk storage in terms of capacity and speed.
Innovation Solution
A nanowire-based Phase Change Material (PCM) memory device is developed, where a semiconductor nanowire with a doping profile forms a field effect transistor (FET) and a p-n junction, surrounded by a phase change material (PCM), allowing for high-density storage by thermally switching the PCM between conductive and insulating states using a small programming current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional non-volatile memory technologies (MRAM, FLASH, FeRAM) are used, then data retention and non-volatility are achieved, but storage density remains limited and cannot reach ultra-high densities
Solution Approach 1:
The patent transitions from planar memory cell layouts to a three-dimensional vertical nanowire structure. The nanowire extends vertically from the substrate with the PCM wrapped around it, enabling storage density improvements by utilizing the vertical dimension rather than only horizontal plane expansion.
Solution Approach 2:
The phase change material is wrapped around the nanowire in a concentric configuration, with the nanowire core containing the FET and p-n junction, and the PCM forming an outer layer. This nested structure maximizes the use of available space and enables ultra-high density packaging.
2Quantity of substance
If higher storage densities are achieved using conventional memory structures, then capacity increases, but power consumption increases and moving parts are required
Solution Approach 1:
The patent eliminates mechanical moving parts by using a solid-state nanowire structure with electrical control. Data is written and read through electrical current pulses that trigger phase changes in the PCM, replacing mechanical actuation with purely electrical and thermal fields.
Solution Approach 2:
The memory stores data by exploiting the phase transition of the PCM between crystalline and amorphous states. Low-power current pulses induce localized heating that triggers these phase transitions, enabling non-volatile storage without requiring continuous power or mechanical components.
3Reliability
If conventional PCM memory structures are used, then non-volatile storage is achieved, but the programming current requires high power consumption
Solution Approach 1:
The patent implements localized heating through the p-n junction positioned at the center of the PCM. The junction generates heat locally at the nanowire core, which then diffuses outward to the PCM, enabling precise thermal control with minimal power consumption. This localized approach avoids the need for high-power uniform heating.
Solution Approach 2:
The nanowire acts as an intermediary thermal conduit between the p-n junction heat source and the surrounding PCM. The nanowire efficiently transfers the generated heat to the PCM, enabling indirect thermal coupling that reduces the overall power requirement compared to direct heating of the PCM.
4Quantity of substance
If storage density is increased to compete with disk storage, then capacity approaches high volumes, but the memory cell footprint must be aggressively reduced
Solution Approach 1:
The patent achieves ultra-high density by moving from two-dimensional planar cells to three-dimensional vertical structures. The nanowire extends vertically with circumferential PCM wrapping, effectively utilizing the vertical dimension to pack more storage elements into a given footprint area.
Solution Approach 2:
The phase change material forms a thin film wrapped around the nanowire in a flexible concentric configuration. This thin-film approach minimizes the radial space required while maintaining sufficient PCM volume for reliable phase transitions, thereby reducing the overall cell footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a high memory density of 10 GB/cm² with extremely low write power of about 10 μW, enhancing storage capacity and reducing power consumption, making it suitable for compact, low-power devices.
Implementation Method 1
coupling one or more selected data lines to a positive voltage so as cause a programming current to flow through each p-n junction corresponding to a selected control line and a selected data line
Implementation Method 2
The GST material is interconvertible between two discrete states, amorphous (high electrical resistance) and crystalline (low electrical resistance), thereby enabling data storage therein. The interconversion or write process is done by thermal cycling of the PCM.
Data Source
AI summary
A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.