Ion-Implanted Relaxed Buffer for Strain Compensation
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Solution Overview
Problem
Current techniques for increasing charge carrier mobility in transistors, particularly in non-planar configurations with sub-100 nanometer gate lengths, face limitations due to poor mechanical coupling between channel and source/drain regions, and the use of a Si substrate restricts strain imposition, leading to suboptimal performance in CMOS applications where different strain values are required for NMOS and PMOS devices.
Innovation Solution
The formation of transistors with diverse and strained channel materials using an ion-implanted relaxed buffer layer, such as a germanium-based layer with inverse-graded Ge concentration, which traps defects near the substrate interface and compensates for strain, allowing for the growth of thick layers without wafer bowing and maintaining strain throughout the channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick relaxed buffer layer is used to prevent defect propagation into the channel, then channel quality is improved, but wafer bowing occurs during downstream fabrication processing
Solution Approach 1:
Ion implantation is performed on the relaxed buffer layer before channel formation to pre-compensate for strain and counteract the wafer bowing that would otherwise occur during downstream processing. This preliminary action prevents the shape distortion before it affects fabrication.
Solution Approach 2:
The strain state of the relaxed buffer layer is modified by ion implantation, changing the mechanical parameters of the buffer layer to achieve strain compensation. This allows the buffer to maintain its thickness for defect blocking while preventing wafer bowing through altered strain characteristics.
2Shape
If a thin relaxed buffer layer is used to avoid wafer bowing, then wafer flatness is maintained, but defects from the layer propagate into the channel
Solution Approach 1:
Ion implantation is applied to the thin buffer layer to pre-compensate for strain, enabling the layer to remain thin for wafer flatness while the ion-induced strain compensation prevents defect propagation into the channel during subsequent processing.
Solution Approach 2:
By changing the strain parameters of the thin buffer layer through ion implantation, the layer can maintain its thin profile for wafer flatness while acquiring enhanced strain compensation properties that prevent defect propagation.
3Reliability
If strain is imposed on the channel to increase charge carrier mobility, then device performance is improved, but mechanical coupling between channel and source/drain regions becomes insufficient in non-planar configurations
Solution Approach 1:
The relaxed buffer layer serves as an intermediary between the channel and the substrate, providing strain compensation that enables strain imposition on the channel while maintaining mechanical integrity. The ion-implanted buffer acts as a mediator that decouples the mechanical stress requirements.
Solution Approach 2:
By modifying the strain parameters of the buffer layer through ion implantation, the mechanical coupling between channel and source/drain regions is enhanced, enabling effective strain imposition on the channel even in non-planar configurations where direct coupling would be insufficient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables significant gains in hole and electron mobility for PMOS and NMOS devices respectively, improving device performance by allowing for the co-integration of high-performance PMOS and NMOS transistors in CMOS circuits with reduced leakage and higher drive currents.
Implementation Method 1
ion-implanted relaxed buffer layer
Implementation Method 2
compensates for strain
Data Source
AI summary
In one embodiment, an integrated circuit includes a substrate, a buffer layer, a source region, a drain region, a channel region, and a gate structure. The substrate includes silicon. The buffer layer is above the substrate and includes a semiconductor material having defects near an interface with the substrate. The buffer layer also includes ions implanted among the defects. The source region and drain region are above the buffer layer, and the channel region is above the buffer layer and between the source and drain regions. The gate structure above the channel region.