Auto-Adjusted Bistable Circuit Timing for Reliable Node Discharge
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing bistable circuits, such as flip-flops, face challenges in maintaining a long enough transparency window for data transfer due to mismatches in transistor characteristics, leading to inefficient discharge of the intermediate node M, which can result in a defective operation and increased holding time for input data.
Innovation Solution
The bistable circuit incorporates a modified inverter chain with a series of nMos transistors replicating the discharge path, allowing for temporal adjustment of the delay to match the discharge time of the intermediate node, ensuring reliable data transfer and reducing the impact of transistor mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If a delay chain based on CH inverters is used to define a time window, then the transparency window duration is extended, but the delay may not be sufficient to allow complete discharge of the intermediate node when transistor mismatches occur
Solution Approach 1:
The patent applies dynamics by making the delay chain adjustable rather than fixed. The delay chain's duration can be dynamically adapted to match the discharge time of the intermediate node, allowing the system to optimize the transparency window duration based on actual discharge requirements. This resolves the contradiction by enabling the delay to be extended when needed while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of delay duration to match the discharge time of the intermediate node. By adjusting the delay chain's timing characteristics to correspond with the transistor discharge time, the system ensures that the transparency window is sufficiently long while guaranteeing complete discharge even with transistor mismatches, thus resolving the contradiction between duration and reliability.
2Reliability
If the delay chain is made longer to ensure sufficient discharge time, then the transparency window is extended, but the holding time for input data increases
Solution Approach 1:
The patent uses dynamics to create an adjustable delay chain that can be optimized for different operating conditions. Rather than using a fixed long delay chain that always extends holding time, the system dynamically adjusts the delay to match the actual discharge time, ensuring reliability while minimizing unnecessary holding time extensions.
Solution Approach 2:
The patent changes the delay parameter to precisely match the discharge time requirement. By tuning the delay chain's duration to correspond exactly with the time needed for complete discharge, the system achieves reliable discharge without unnecessarily extending the holding time, thus resolving the contradiction between discharge reliability and time loss.
3Reliability
If transistor size ratios are adjusted to compensate for mismatches, then discharge reliability improves, but the delay chain timing becomes difficult to match with discharge time
Solution Approach 1:
The patent applies dynamics by using an adjustable delay chain that can be tuned to match the discharge time resulting from the transistor size ratios. This dynamic adjustment capability allows the system to maintain both discharge reliability (through consistent transistor sizing) and timing alignment (through adjustable delay), resolving the contradiction between reliability and complexity.
Solution Approach 2:
The patent changes the delay parameter to match the discharge time established by the transistor size ratios. By making the delay chain adjustable, the system can compensate for the timing effects of consistent transistor sizing, thereby maintaining discharge reliability while simplifying the timing alignment process and reducing overall device complexity.
Data Source
AI summary
Bistable circuit switching at the edges of a clock signal, including means for pre-charging an intermediate node of the circuit, delay means including a chain of inverters defining a time window around an edge of said clock signal, means for discharging the intermediate node controlled by at least one input data item making it possible to discharge the intermediate node for the duration of said time window, characterized in that the delay means include means for temporally adjusting the duration of the time window to the time for discharging the intermediate node through said discharge means.