Bit-Cell Array Decoupling Capacitors for Dense Power Rails
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Solution Overview
Problem
The increasing density and shrinking size of integrated circuits require higher capacitance per area rate, fewer front-end device usage, lower leakage current, and fewer back-end metal usage for power and ground bounce reduction in power delivery networks.
Innovation Solution
The integration of stacked bit-cell arrays in semiconductor devices, where each array provides decoupling capacitance through bit lines and plate lines, enhancing voltage tolerance and capacitance, and the inclusion of a control circuit for testing and repairing defective sub-arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional decoupling capacitors are used in power delivery networks, then power and ground bounce can be reduced, but the capacitance per area rate is insufficient for increasing circuit density
Solution Approach 1:
The patent merges the decoupling capacitor function with the memory array structure by utilizing the bit line and plate line as capacitor terminals. The memory array serves dual purposes: data storage and power delivery network decoupling, eliminating the need for separate decoupling capacitor structures and achieving high capacitance per area rate
Solution Approach 2:
The memory array is designed to perform multiple functions simultaneously: data storage, data access operations, and power delivery network decoupling. The bit line and plate line serve both as memory access lines and as capacitor terminals, enabling the same structure to fulfill multiple roles without additional area overhead
2Quantity of substance
If more front-end devices are used to increase capacitance, then decoupling performance improves, but device complexity and front-end usage increase
Solution Approach 1:
The patent combines the decoupling capacitor with the memory array structure, using the existing bit line and plate line as capacitor terminals. This eliminates the need for additional front-end devices and achieves high capacitance without increasing device complexity
Solution Approach 2:
The memory array structure serves itself by providing decoupling capacitance through its inherent bit line and plate line, without requiring external decoupling capacitors or additional front-end control devices. The same structure that stores data also provides power delivery network stabilization
3Quantity of substance
If stacked bit-cell arrays are integrated to increase capacitance, then voltage tolerance and capacitance improve, but manufacturing and testing complexity increases
Solution Approach 1:
The patent merges multiple bit-cell arrays in a stacked configuration where each array contributes to the total decoupling capacitance. The bit lines and plate lines of stacked arrays are connected in parallel to form a large-capacitance decoupling structure, achieving high capacitance values without requiring complex three-dimensional packaging or additional manufacturing steps
Solution Approach 2:
The stacked bit-cell arrays serve dual functions: data storage in memory mode and decoupling capacitance in capacitor mode. The same stacked structure that provides increased storage capacity also provides proportionally increased decoupling capacitance, maintaining manufacturing simplicity while achieving both goals
4Reliability
If stacked bit-cell arrays are used for decoupling, then voltage tolerance increases, but the ability to detect and measure defective sub-arrays becomes more difficult
Solution Approach 1:
The patent incorporates test circuits that apply test voltages to the stacked bit-cell arrays and measure the resulting currents or voltages to detect defective sub-arrays. The feedback mechanism allows identification of specific defective arrays among the stacked configuration, enabling selective repair or replacement while maintaining the overall high voltage tolerance of the stacked structure
Solution Approach 2:
The stacked bit-cell arrays are divided into individually addressable sub-arrays, each with its own bit lines and plate lines. This segmentation allows defective sub-arrays to be identified and isolated through selective activation and measurement, making defect detection feasible even in the stacked configuration while maintaining high voltage tolerance through the remaining functional sub-arrays
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides increased voltage tolerance and capacitance, allowing for efficient power delivery while enabling effective testing and repair of defective sub-arrays, thus optimizing performance and reliability in high-bandwidth memory and high-speed computation circuits.
Implementation Method 1
the first bit-cells are configured as a decoupling capacitor between the first and second power rails for the circuit
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a circuit and a first bit-cell array. The circuit is coupled to a first power rail and a second power rail. The first bit-cell array comprises a first sub-array having multiple first bit-cells that are coupled between the first power rail and the second power rail. The first bit-cells are configured as a decoupling capacitor between the first and second power rails for the circuit in response to a first operational voltage on the first power rail and a second operational voltage on the second power rail.