Bit-Dependent Pulse-Width Equalizer for ISI in Memory Signals

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Semiconductor memory devices face challenges in maintaining data transmission speed and reliability due to signal distortion caused by inter symbol interference (ISI) in data signals.

Innovation Solution

An equalizer is designed to remove ISI by increasing the pulse width corresponding to each logic level of the data signal, utilizing pulse width controllers, samplers, and multiplexers to process and output sampled signals based on previous data bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If signal transmission speed is increased, then productivity is improved, but signal distortion and inter symbol interference worsen

Engineering Contradiction:

Improvedata transmission speedVSAvoidsignal quality

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The equalizer performs preliminary compensation for inter symbol interference before data sampling. By adjusting the pulse width of the data signal in advance based on previous data bits, the signal is pre-conditioned to prevent distortion accumulation, thereby maintaining signal quality at high transmission speeds

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The equalizer uses feedback from previous data bits to adjust the current data signal. The pulse width controller receives information about previously transmitted bits and uses this feedback to compensate for expected interference in the current signal, creating a closed-loop system that maintains reliability at high speeds

Inventive Principle:

Principle #23Feedback

2Reliability

If pulse width is increased to remove inter symbol interference, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvedata identification accuracyVSAvoidequalizer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The equalizer is divided into separate functional modules: a pulse width controller that adjusts signal duration, a sampler that captures data at optimal moments, and a multiplexer that selects between different signal paths. This segmentation allows each component to perform its function efficiently without requiring complex integrated design

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The pulse width controller acts as an intermediary between the data signal source and the sampler. It mediates the signal by adjusting pulse widths based on previous data bits, creating an intermediate conditioned signal that is easier to sample accurately without requiring complex sampling circuitry

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12301236B2Equalizer for removing inter symbol interference of data signal by increasing pulse widths of logic low level and logic high level of data signal

Publication Date: 2025.05.13 SAMSUNG ELECTRONICS CO LTD

AI summary

An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.