Bit Line Boundary Structure for Buried Contact Reliability

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Solution Overview

Problem

As semiconductor elements become highly integrated, the complexity of forming wiring lines and buried contacts increases, requiring precise structure configurations and processes to ensure reliable structures, which existing technologies struggle to achieve effectively.

Innovation Solution

A semiconductor device with a substrate having a cell region and a core region separated by a boundary element separation film, featuring a bit line that extends along a specific direction over different height regions of the film, and includes a buffer layer and capping films to enhance contact areas and reduce contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor elements are highly integrated and miniaturized, then more elements can be integrated in a small area, but the process complexity of forming wiring lines and buried contacts increases significantly

Engineering Contradiction:
Improveintegration densityVSAvoidprocess complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The boundary element separation film is divided into multiple regions with different heights, creating distinct structural zones that simplify the formation process of wiring lines and buried contacts in highly integrated semiconductor devices

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention introduces height variation in the boundary element separation film, transitioning from a two-dimensional planar structure to a three-dimensional multi-level structure, enabling improved integration without proportionally increasing process complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If the boundary element separation film has uniform height, then the structure is simple to manufacture, but the contact area and electrical performance are limited

Engineering Contradiction:
Improvestructural simplicityVSAvoidcontact reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Different regions of the boundary element separation film are assigned different heights to optimize local contact properties, with first regions providing larger contact areas for bit lines and second regions offering appropriate contact areas for core region wiring lines, thereby improving overall contact reliability

Inventive Principle:
Principle #3Local quality

3Device complexity

If the bit line contacts the boundary element separation film directly, then the manufacturing process is simpler, but the contact resistance is high and reliability is reduced

Engineering Contradiction:
Improveprocess complexityVSAvoidcontact resistance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

A buffer layer is introduced as an intermediary between the bit line and the boundary element separation film, improving electrical contact properties and reducing contact resistance while maintaining manufacturing feasibility

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12052856B2Semiconductor device
Publication Date: 2024.07.30 SAMSUNG ELECTRONICS CO LTD
  • US12052856B2 patent drawing
  • US12052856B2 patent drawing
  • US12052856B2 patent drawing

AI summary

A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region and a core region, a boundary element separation film which is placed inside the substrate, and separates the cell region and the core region, and a bit line which is placed on the cell region and the boundary element separation film and extends along a first direction, in which the boundary element separation film includes a first region and a second region, a height of an upper side of the first region of the boundary element separation film is different from a height of an upper side of the second region of the boundary element separation film, on a basis of a bottom side of the boundary element separation film, and the bit line is placed over the first region and the second region of the boundary element separation film.