Bit Line Charging Control Circuit for Memory Arrays
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Solution Overview
Problem
High density memory devices face challenges in controlling bit line charging current due to variations in data patterns and capacitive coupling, leading to peak current fluctuations and inefficient charging speeds.
Innovation Solution
A control circuit that regulates bit line charging current using a ramp function and feedback mechanisms to maintain consistent current flow, employing bit line clamp transistors and a voltage ramp generator to adjust the bit line control signal based on sensed load, ensuring uniform charging across all bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are pre-charged to inhibit programming, then programming inhibition is achieved, but peak current levels increase and charging speed varies
Solution Approach 1:
The patent applies dynamics by making the bit line control signal time-varying through a ramp function. Instead of applying a static pre-charge voltage, the control signal gradually increases from an initial voltage to a final voltage over the charging interval. This dynamic approach allows the current to be distributed over time, preventing peak current spikes while still achieving the necessary bit line charging for programming inhibition.
Solution Approach 2:
The patent changes the voltage parameter of the bit line control signal as a function of time using a ramp function. The signal transitions from an initial voltage level to a final voltage level during the charging interval, thereby controlling the current flow dynamically. This parameter change enables consistent charging speed across varying loads while limiting peak current levels.
2Reliability
If bit lines are pre-charged to inhibit programming, then programming inhibition is achieved, but charging speed varies with data pattern
Solution Approach 1:
The ramp function control signal dynamically adjusts the charging process. By gradually increasing the control voltage, the system maintains a consistent charging speed regardless of the data pattern. The dynamic nature of the ramp function allows the charging process to adapt to varying capacitive loads while maintaining uniform timing characteristics.
3Device complexity
If conventional bit line charging is used, then simplicity is maintained, but current fluctuations and inconsistent charging occur
Solution Approach 1:
The patent employs feedback by sensing the actual current flowing during bit line charging and using this information to adjust the ramp function parameters. The feedback mechanism monitors the charging process and modifies the control signal to maintain consistent current flow, thereby stabilizing the charging operation across varying data patterns and loads.
Data Source
AI summary
A memory device includes a memory array and bit lines coupled to the memory array. A voltage source is included for supplying a voltage used during a charging operation. Bit line clamp transistors, such as bit line clamp transistors, are coupled to the voltage source, and configured to regulate current on the corresponding bit lines in response to a bit line control signal. A control circuit generates the bit line control signal in response to a feedback signal. A feedback circuit is provided that is coupled to the voltage source and produces the feedback signal. The feedback circuit senses load of the bit lines being charged. The load of the bit lines being charged can be sensed by sensing the magnitude of the current from the voltage source during the charging operation.