Read-Only Memories TRIZ Cases
- Negative Voltage Wordline via Capacitive Coupling
Capacitive coupling shifts selected wordlines to negative voltage, eliminating complex generator circuitry and improving data retention margins.
- Semiconductor Memory Voltage Control for Write Uniformity
A semiconductor memory device adjusts voltage supply lines based on active write planes to ensure uniform voltage rise characteristics across all memory blocks.
- Nonvolatile Memory Index Cell Threshold Voltage Compensation
Index cells track threshold voltage drift to dynamically adjust read voltages, reducing errors caused by cell wear and coupling effects.
- Volatile Memory Cell Array for Nonvolatile Storage Erase Control
A volatile memory cell array stores erase setting information using dedicated readout amplifiers, reducing circuit area required for latch circuits.
- Nonvolatile Memory Programming Method for Multi-Level Cell Speed
A nonvolatile memory programming method controls program pulses and verification operations to manage current consumption.
- Non-Volatile Memory Temperature-Aware Data Scrubbing
Records temperature codes in spare cells to adjust read voltages, reducing bit error rates caused by cross-temperature effects.
- Multilevel Flash NAND Memory Cell Programming for Safety Margin
Segmented programming of first and second bits in a selected cell increases safety margins between contiguous threshold voltage distributions.
- Flash Memory Cell Programming via Segmented Two-Phase Voltage Shifting
Segmenting flash memory cell programming into distinct phases minimizes capacitive coupling interference while maintaining high storage density.
- Selective Column Pre-Charging in Memory Circuits
A memory circuit uses column pre-decoding to selectively pre-charge targeted bit lines during data access.
- Sense Amplifier Single Phase Signal Design
A sense amplifier uses a single phase signal to stabilize comparison voltages across internal stages.
- Nonvolatile Memory Circuit Area Reduction via Segmented Drive
Independent voltage switches for selective transistor drives reduce circuit area while maintaining two-bit storage capability in MONOS memory cells.
- DIMM SSD SoC Byte Lane Skewing for Memory Controller Compatibility
A DIMM SSD SoC uses variable delay elements to simulate board channel skew, resolving signal integrity issues and maximizing bus frequency.
- Vertical Stack Memory Device Oxygen Scavenger Layers
Oxygen scavenger layers form vacancies in recording material to enhance resistance change characteristics, addressing unit cell scaling limits.
- Bit Line Charging Control Circuit for Memory Arrays
A control circuit regulates bit line charging current using ramp functions and feedback mechanisms to maintain consistent operation.
- Sense Amplifier Equalizing Transistor NAND Flash
A sense amplifier uses an equalizing transistor to prepare output nodes before sensing operations begin.
- Flash Memory Pre-charge Voltage Control
A pre-charge voltage system regulates pulse width and height to stabilize memory lines.