Multilevel Flash NAND Memory Cell Programming for Safety Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multilevel flash NAND memory devices face reliability issues due to reduced safety margins between threshold voltage distributions, particularly when reading data that requires high precision, such as in the 'sector 0' which stores boot information, as existing solutions do not effectively exploit the increased design complexity to enhance memory reliability beyond access speed.
Innovation Solution
The method involves programming a first bit in a selected cell by shifting it from a first threshold level to a second level, and separately programming a second bit by preliminary reading to determine if the first bit has been modified, then writing the cell to a third or fourth threshold level based on the modification, using a multilevel nonvolatile memory device with a safe portion employing outermost threshold voltage distributions for increased reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilevel memory stores four threshold voltage levels in each cell, then storage capacity increases, but safety margins between contiguous threshold voltage distributions decrease
Solution Approach 1:
The patent segments the programming process into two independent operations: programming the first bit (MSB) and separately programming the second bit (LSB). This segmentation allows each bit to be programmed with dedicated threshold voltage shifts, effectively creating separate programming paths that maintain larger safety margins between threshold distributions while still achieving 2-bit storage capacity.
Solution Approach 2:
The patent introduces a temporal dimension by performing preliminary reading before the second programming operation. This additional time step allows the system to detect whether the first bit was modified during programming, and conditionally adjust the second bit's threshold voltage accordingly, thereby maintaining safety margins that would otherwise be reduced in conventional simultaneous programming approaches.
2Reliability
If substitution algorithms are used to remap sector 0 content, then data redundancy is achieved, but reading accuracy and reliability remain unchanged
Solution Approach 1:
The patent applies local quality by using different programming strategies for different bits within the same cell. The first bit (MSB) and second bit (LSB) are programmed with different threshold voltage shifts and different programming conditions, creating locally optimized threshold distributions that maximize safety margins for each bit while maintaining overall 2-bit storage capacity.
Solution Approach 2:
The patent performs a preliminary reading operation before programming the second bit to determine whether the first bit has been modified. This preliminary action allows the system to conditionally adjust the programming of the second bit, ensuring that the final threshold voltage distribution maintains adequate safety margins regardless of the first bit's state, thereby improving reading accuracy without sacrificing redundancy.
Data Source
AI summary
Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.