Semiconductor Memory Voltage Control for Write Uniformity
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing voltage supply during write operations across multiple memory blocks, leading to inconsistent voltage rise characteristics and varying write performance due to differing write plane numbers.
Innovation Solution
The semiconductor memory device employs a voltage generation control circuit that adjusts output voltages and connects variable capacitance circuits with the voltage supply lines based on the number of memory cell arrays undergoing write operations, ensuring uniform voltage rise characteristics across all memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed voltage supply method is used for multiple memory blocks, then the circuit design is simple, but the voltage rise characteristics become inconsistent across different write plane numbers
Solution Approach 1:
The patent implements dynamic voltage supply control where the voltage generation control circuit adjusts the output voltage level based on the detected write plane number. The system transitions from a static fixed voltage supply to a dynamic adaptive voltage supply that changes parameters in real-time according to operational conditions, ensuring consistent voltage rise characteristics across different write scenarios.
Solution Approach 2:
The patent changes the voltage parameter (output voltage level) based on the write plane number detected by the voltage generation control circuit. By adjusting the voltage parameter dynamically - using higher voltages for single-plane writes and lower voltages for multi-plane writes - the system achieves uniform voltage rise characteristics without requiring complex circuit reconfiguration.
2Productivity
If voltage is supplied to all memory blocks simultaneously, then the write operation can proceed in parallel, but the voltage rise characteristics become inconsistent due to differing write plane numbers
Solution Approach 1:
The patent applies local quality by providing different voltage levels to different memory blocks based on their specific write plane configuration. The voltage generation control circuit detects which planes are being written and supplies appropriately differentiated voltage levels - higher voltages to blocks requiring more drive strength and lower voltages to blocks that don't need excessive voltage headroom, ensuring each block receives optimal voltage for its specific operational context.
Solution Approach 2:
The system maintains parallel write operations while achieving consistent voltage rise characteristics by dynamically changing the voltage parameter for each memory block based on its write plane number. This allows simultaneous writes to multiple blocks with differentiated voltage levels, optimizing both productivity and reliability.
3Productivity
If the output voltage is fixed regardless of write plane number, then the power consumption is stable, but the write performance varies across different memory blocks
Solution Approach 1:
The patent changes the voltage parameter dynamically based on the write plane number to achieve uniform write performance across all memory blocks. By supplying higher voltages when fewer planes are active and lower voltages when more planes are active, the system maintains consistent write performance while allowing power consumption to vary adaptively rather than remaining fixed.
Solution Approach 2:
The system transitions from static fixed voltage supply to dynamic voltage supply that adapts to the write plane number. This dynamic approach ensures uniform write performance across different operational scenarios while accepting that power consumption will vary based on the actual write workload and plane configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent and uniform voltage rise characteristics during write operations, improving the reliability and efficiency of data storage across multiple memory blocks by adapting voltage outputs and capacitance charging based on the write plane number.
Implementation Method 1
the voltage generating circuit is supplied with a first voltage at a first timing in the write operation. In the case of the write operation being executed on any one of the plurality of first memory blocks and not being executed on any one of the plurality of second memory blocks, a variable capacitance circuit is connected with the voltage supply line at the first timing
Data Source
AI summary
ABSTRACT A semiconductor memory device provides a first memory cell array including a plurality of first memory blocks, a second memory cell array comprising a plurality of second memory blocks, and a voltage supply line electrically connected to the plurality of first memory blocks and the plurality of second memory blocks. Moreover, this semiconductor memory device is configured to execute a write operation. At a first timing of this write operation, the voltage supply line is not electrically continuous with the first and second memory blocks. Moreover, a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first and second memory blocks is larger than a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first memory block.