Flash Memory Cell Programming via Segmented Two-Phase Voltage Shifting
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Solution Overview
Problem
Interference between memory cells in flash memory devices, specifically due to capacitive coupling, becomes more significant as device scaling reduces, affecting the programming process and accuracy, particularly in Multi-Layer Cell (MLC) memory where increased voltage distributions lead to higher interference.
Innovation Solution
Implementing a two-phase programming process where the lower page of memory cells is programmed first, followed by the upper page, with simultaneous compaction of the erased distribution to reduce voltage changes and minimize capacitive coupling, thereby decreasing interference between floating gate transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to increase density, then storage capacity is improved, but capacitive coupling between cells increases causing more interference
Solution Approach 1:
The patent segments the programming operation into two distinct phases: a first programming phase that programs a first page of memory cells, and a second programming phase that programs a second page of memory cells. This segmentation allows interference from cells programmed in the first phase to settle before cells in the second phase are programmed, thereby reducing the harmful capacitive coupling effects while maintaining high storage capacity through continued scaling.
2Productivity
If programming voltage is increased to improve programming speed, then productivity is improved, but interference between floating gate transistors increases
Solution Approach 1:
The programming operation is divided into two phases with different voltage characteristics. The first programming phase uses higher voltages to achieve fast programming of the first page, while the second programming phase uses lower voltages to program the second page after interference has settled. This segmentation maintains high overall productivity while reducing Fg-Fg interference through temporal separation of high-voltage operations.
Solution Approach 2:
The patent implements periodic action by alternating between programming operations on different pages of memory cells. After completing programming of the first page, the system waits for interference to subside before initiating programming of the second page. This periodic approach allows high-voltage programming to occur in controlled intervals, maintaining productivity while limiting cumulative interference effects.
3Quantity of substance
If multi-layer cell structure is used to increase storage density, then quantity of substance is improved, but voltage distribution complexity increases leading to higher interference
Solution Approach 1:
The patent applies segmentation by dividing the memory array into distinct pages (first page and second page) that can be programmed separately in different phases. This segmentation simplifies the voltage distribution complexity inherent in multi-layer cell structures by allowing controlled, phased programming operations rather than simultaneous programming of all cells, thereby reducing interference while maintaining high storage density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces Fg-Fg interference by minimizing the voltage change required for upper page programming, leading to more efficient and faster programming processes with reduced capacitive coupling, enhancing the accuracy and reliability of memory cell programming.
Implementation Method 1
interference based on the changing voltage and capacitive coupling between nearby cells
Implementation Method 2
programming a cell entails bringing that particular cell up to a specified voltage, Vt
Data Source
AI summary
Embodiments of the inventive subject matter provide systems and methods for programming a set of memory cells by inducing a first voltage on the lower page of a first group of memory cells to hold a first least significant bit, and by inducing a second voltage on the lower page of a second group of memory cells to hold a second least significant bit. Once the lower page is programmed, the voltage may be shifted to the upper page of each memory cell into a final range representing one or more most significant bits to be programmed. Each memory cell may store a voltage within a final programmed range representing a binary value.