Nonvolatile Memory Circuit Area Reduction via Segmented Drive
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Solution Overview
Problem
Nonvolatile semiconductor memory devices with MONOS memory cells using a virtual ground face challenges in reducing the circuit area due to the need for high voltage tolerance in selective transistors, which increases layout area and complexity, especially when storing two-bit information.
Innovation Solution
The implementation of a nonvolatile semiconductor memory device with independently selectable voltage switches for selective transistor drive circuits allows for the use of transistors with lower voltage tolerance, reducing the circuit area by optimizing voltage settings for one-bit information storage, thereby minimizing the layout area required for the drive circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high voltage tolerance transistors are used for selective transistor drive circuits to enable two-bit information storage, then the memory cell functionality is improved, but the circuit area and layout complexity increase
Solution Approach 1:
The patent divides the bit line configuration into two separate groups: first bit lines (BL0, BL2, ...) connected to first diffusion layers and second bit lines (BL1, BL3, ...) connected to second diffusion layers. This segmentation allows independent voltage control of each group, enabling the use of lower voltage tolerance transistors in the drive circuits while maintaining two-bit storage capability through differential voltage application.
Solution Approach 2:
The patent applies different voltage levels to different parts of the memory array: first bit lines receive one voltage level while second bit lines receive another voltage level. This local quality differentiation allows selective charge injection into specific MONOS films adjacent to either first or second diffusion layers, enabling two-bit storage without requiring all transistors to tolerate high voltages simultaneously.
2Adaptability or versatility
If high voltage tolerance transistors are used for selective transistor drive circuits, then the program operation for two-bit storage is enabled, but the device complexity increases
Solution Approach 1:
The drive circuit is segmented into separate control paths for first bit lines and second bit lines. First selective transistor groups control first bit lines while second selective transistor groups control second bit lines. This segmentation simplifies the complexity by allowing independent, optimized design of each control path rather than requiring all transistors to handle maximum voltage.
Solution Approach 2:
The memory cell structure is designed to be multi-functional: the same MONOS memory cell can store different information bits by applying different voltage combinations to the first and second bit lines. This universality allows a single cell structure to perform multiple storage functions without increasing transistor voltage tolerance requirements.
3Quantity of substance
If two-bit information is stored in one memory cell, then the storage density is improved, but the probability of erroneous read operations increases
Solution Approach 1:
The patent creates distinct local regions within the memory cell: first diffusion layers with adjacent MONOS films for storing one bit, and second diffusion layers with adjacent MONOS films for storing another bit. This local quality differentiation physically separates the two bits, reducing interference and improving read accuracy while maintaining high storage density.
Solution Approach 2:
The memory cell is segmented into functionally distinct regions: first bit storage regions connected to first bit lines and second bit storage regions connected to second bit lines. This segmentation allows independent verification and reading of each bit, improving reliability by enabling error detection and correction mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a reduced circuit area for nonvolatile semiconductor memory devices, improving reliability and efficiency by allowing the use of lower voltage tolerance transistors, which decreases the probability of erroneous read operations and reduces the overall size and cost of the memory device.
Implementation Method 1
hot electrons generated by a current flowing through the channel are injected into the charge injection area A1
Data Source
AI summary
Bit lines connected to each nonvolatile memory cell are selected by corresponding selective transistors. A first drive circuit for driving the gate of one of the selective transistors receives a voltage selected by a first voltage switch, and a second drive circuit for driving the gate of the other selective transistor receives a voltage selected by a second voltage switch. A transistor constituting the first drive circuit is different in structure from a transistor constituting the second drive circuit.