DIMM SSD SoC Byte Lane Skewing for Memory Controller Compatibility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional memory controllers expect board channel skew in DIMMs, which is not present in DIMM Solid State Drives (SSDs), leading to interoperability issues and signal integrity problems.
Innovation Solution
A DIMM SSD System-on-a-Chip (SoC) with variable delay elements that simulate the board channel skew of traditional DIMMs by delaying signal transmission to mimic the staggered arrival times of signals in DRAM modules, allowing SSDs to interoperate with memory controllers that expect board channel skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DIMM SSD is used without byte lane skewing, then all data can be read and written at the same time (improving speed), but noise is introduced that affects system operation (worsening reliability)
Solution Approach 1:
The patent applies dynamics by making the byte lane skewing configurable and adjustable rather than fixed. The system can dynamically enable or disable skewing based on operational conditions, allowing optimization between speed and reliability depending on the specific use case and noise sensitivity.
Solution Approach 2:
The patent changes the parameter of signal timing by introducing variable skewing to different byte lanes. By adjusting the timing parameters of signal transmission on different lanes, the system can simulate traditional DIMM behavior when needed while maintaining the SSD's inherent speed advantages when skewing is not applied.
2Reliability
If byte lane skewing is applied to DIMM SSD, then compatibility with memory controllers is improved (improving reliability), but signal transmission complexity increases (worsening device complexity)
Solution Approach 1:
The patent uses an intermediary approach by introducing a skewing layer between the SSD controller and the byte lanes. This intermediary component manages the complexity of differential skewing by providing a standardized interface that handles timing adjustments without exposing the underlying complexity to the rest of the system.
Solution Approach 2:
The patent segments the signal transmission path by applying skewing independently to different byte lanes rather than treating all lanes uniformly. This segmentation allows selective timing adjustments on individual lanes, enabling compatibility with memory controllers while keeping the overall system design manageable through modular lane handling.
3Reliability
If traditional DIMM topology is used, then board channel skew is naturally present (improving memory controller compatibility), but signals arrive at different times at DRAM elements (worsening speed)
Solution Approach 1:
The patent inverts the traditional approach by starting with synchronized signal arrival (the SSD's natural state) and then applying controlled skewing to simulate traditional DIMM behavior. Rather than accepting natural skew and trying to compensate, the system begins with perfect synchronization and introduces skewing only where needed for compatibility, effectively doing the opposite of traditional DIMM design.
Data Source
AI summary
A Dual In-Line Memory Module (DIMM) Solid State Drive (SSD) System-on-a-Chip (SoC) (345) is disclosed. The DIMM SSD SoC (345) can interoperate with a host memory controller (335) as though it were a traditional Dynamic Random Access Memory (DRAM) DIMM (105, 130) with system interconnect skew and on-DIMM skew, even though the DIMM SSD SoC (345) does not have on-DIMM skew. The DIMM SSD SoC (345) can include variable delay elements (422, 424, 426, 428, 430, 432, 434, 436, 438) that can replicate the delay a traditional DRAM DIMM (105, 130) experiences and that the host memory controller (335) expects, or a superior delay that minimizes system signal integrity issues, thereby increasing maximum system speed.