Sense Amplifier Equalizing Transistor NAND Flash
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Solution Overview
Problem
Current sense amplifiers in NAND-type flash memories face challenges in detecting small cell currents at high rates due to variations in transistor threshold voltages and gate lengths, leading to difficulties in distinguishing between data levels, especially when the current difference is minimal, which can result in slow sense performance and increased chip area overhead.
Innovation Solution
A current-detecting type sense amplifier is designed with specific transistor configurations, including NMOS and PMOS transistors, a latch structure, and an equalizing transistor to amplify and equalize output nodes, allowing for high-speed detection of small current differences without increasing transistor size, thereby reducing variations and maintaining high sense performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional sense amplifier is used to detect small cell currents, then the chip area can be reduced, but the sense performance becomes slow due to transistor threshold voltage and gate length variations
Solution Approach 1:
The equalizing transistor equalizes the output nodes in potential before sensing begins. This preliminary action removes potential differences caused by transistor variations, allowing the sense amplifier to detect only the actual cell current differences without interference from manufacturing variations, thereby improving both precision and speed
Solution Approach 2:
The latch structure provides positive feedback to amplify the small current differences between cell and reference currents. The feedback mechanism reinforces the signal from the differential pair, converting tiny current differences into significant voltage swings that can be reliably detected, thus improving measurement precision while maintaining high sense speed
2Measurement precision
If transistor size is increased to reduce variations, then sense performance improves, but chip area overhead increases
Solution Approach 1:
Instead of increasing transistor physical size to reduce variations, the patent changes the operational parameters by introducing the equalizing transistor that actively compensates for threshold voltage and gate length variations through potential equalization. This allows small transistors to achieve high precision by dynamically correcting variations rather than relying on large dimensions
Solution Approach 2:
The equalizing transistor acts as an intermediary element that mediates between the differential pair and the output nodes. It removes the harmful effect of transistor variations by equalizing potentials before the sensing operation, allowing the use of smaller transistors while maintaining high measurement precision without increasing chip area
Data Source
AI summary
A sense amplifier includes: NMOS transistors, drains thereof being coupled to output nodes, gates thereof being coupled to the output nodes, sources thereof being coupled in common to the ground potential node; PMOS transistors, drains thereof being coupled to the drains of the NMOS transistors, sources thereof being coupled to the input nodes; PMOS transistors, drains thereof being coupled to the input nodes, gates thereof being coupled to the output nodes, sources thereof being coupled to the power supply node via a current source device; and NMOS transistors disposed between the output nodes and the ground potential node to be turned on before sensing; and an equalizing transistor disposed between the output nodes.