Bit Line Forcing Voltage Clamp Circuit for ISPP Distortion Control
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Solution Overview
Problem
Nonvolatile memory devices face issues with programming performance due to bit line-bit line capacitive coupling effects in all bit line (ABL) architecture, leading to incremental-step-pulse programming (ISPP) distortion and decreased programming efficiency.
Innovation Solution
Incorporating a bit line forcing voltage clamp circuit connected between the bit line and page buffer, utilizing a DC voltage generator to maintain a consistent bit line forcing voltage level, which is adjusted by a transistor to prevent variations caused by neighboring bit lines, thereby controlling the bit line forcing voltage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If all bit line architecture is used to increase memory density, then storage capacity is improved, but bit line-bit line capacitive coupling effects cause ISPP distortion and decrease programming performance
Solution Approach 1:
A bit line forcing voltage clamp circuit is introduced as an intermediary component between the page buffer and the bit line. This clamp circuit acts as a mediator that actively controls and stabilizes the bit line forcing voltage, preventing capacitive coupling effects from neighboring bit lines from causing ISPP distortion while maintaining the high density benefits of ABL architecture
Solution Approach 2:
The invention dynamically adjusts the bit line forcing voltage parameter through the clamp circuit. By changing the voltage level from a fixed value to a controlled parameter that compensates for capacitive coupling effects, the system maintains programming performance across all bit lines in the high-density ABL configuration
2Productivity
If bit line forcing voltage is increased to improve programming speed, then programming efficiency is improved, but ISPP distortion increases due to capacitive coupling effects
Solution Approach 1:
The bit line forcing voltage clamp circuit incorporates feedback mechanisms that continuously monitor and adjust the bit line voltage based on actual capacitive coupling conditions. This feedback control allows the system to maintain optimal programming speed while preventing ISPP distortion by compensating for voltage variations caused by neighboring bit lines
Solution Approach 2:
The clamp circuit applies local control to each bit line's forcing voltage independently. By tailoring the voltage level to the specific conditions of each bit line (accounting for local capacitive coupling effects), the system achieves both high programming speed and uniform threshold voltage distribution without excessive ISPP distortion
Data Source
AI summary
A nonvolatile memory device including a bit line connected to a cell string, a page buffer connected to the bit line, the page buffer is configured to output a target bit line forcing voltage level to the bit line during a programming operation, and a bit line forcing voltage clamp circuit connected between the bit line and the page buffer, and the bit line forcing voltage clamp circuit is configured to adjust the target bit line forcing voltage level to the bit line.