Semiconductor Bit Line Interconnections with Reduced Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices integrate more densely, the horizontal interval between metal interconnections decreases, leading to increased parasitic capacitance between electrically isolated metal interconnections, which affects device performance.
Innovation Solution
The semiconductor devices feature bit line interconnections that form contacts with drain regions having a greater width and lower level than those that do not, with specific conductive patterns and masking processes used to create tab structures and varying heights to reduce parasitic capacitance and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the horizontal interval between adjacent metal interconnections is reduced to increase integration density, then the integration density is improved, but the parasitic capacitance between metal interconnections increases
Solution Approach 1:
The patent introduces a vertical dimension to solve the horizontal spacing problem. By forming bit line interconnections at different heights (first bit line interconnection at a first height, second bit line interconnection at a second height), the design transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. This dimensional change allows adjacent bit lines to be closely spaced horizontally while maintaining electrical isolation through vertical separation, thereby increasing integration density without significantly increasing parasitic capacitance between adjacent bit lines.
Solution Approach 2:
The patent segments the bit line interconnections into multiple distinct layers or levels. The first bit line interconnection and second bit line interconnection are formed as separate conductive structures at different heights, with insulating layers between them. This segmentation allows each bit line to be independently routed and controlled, reducing unwanted capacitive coupling while maintaining high density through efficient use of vertical space.
2Reliability
If the width of bit line interconnections is increased to reduce contact resistance, then the contact resistance is improved, but the area occupied by bit line interconnections increases
Solution Approach 1:
The patent resolves the conflict between contact resistance and area by utilizing the vertical dimension. The first bit line interconnection is positioned at a first height and the second bit line interconnection at a second height, allowing both to share the same horizontal footprint without excessive capacitive coupling. This vertical stacking enables sufficient contact area for low resistance while minimizing the planar area occupied, thereby maintaining high integration density.
Solution Approach 2:
The patent implements a nested arrangement where bit line interconnections are positioned one above the other in a vertical stack. The first bit line interconnection and second bit line interconnection are nested at different heights, with each occupying a portion of the same horizontal space. This nesting strategy maximizes the use of three-dimensional space, allowing multiple interconnections to coexist in a compact area while maintaining adequate contact dimensions for low resistance.
Data Source
AI summary
A semiconductor device has a bit line interconnection with a greater width and a reduced level on a bit line contact is provided, as are methods of fabricating such devices. These method includes forming a buried gate electrode to intersect an active region of a substrate. Source and drain regions are formed in the active region. A first conductive pattern is formed on the substrate. The first conductive pattern has a first conductive layer hole configured to expose the drain region. A second conductive pattern is formed in the first conductive layer hole to contact the drain region. A top surface of the second conductive pattern is at a lower level than a top surface of the first conductive pattern. A third conductive layer and a bit line capping layer are formed on the first conductive pattern and the second conductive pattern and patterned to form a third conductive pattern and a bit line capping pattern. The second conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the drain region, constitute first bit line structures, and the first conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the isolation region, constitute second bit line structures.