Bit Line Switching Circuit for Faster Low-Voltage Memory Biasing
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Solution Overview
Problem
Memory circuits operate at reduced speeds due to low operating voltages, which limit power consumption and generate heat, and existing solutions to increase memory access speeds are complex and power-intensive.
Innovation Solution
A switching circuit is introduced to enhance bit line biasing by increasing current availability, allowing bit lines to reach bias voltage levels more rapidly, thereby improving operating speed without additional complexity or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory circuits are operated at low voltages to limit power consumption and heat generation, then power consumption and heat generation are reduced, but circuit speeds and memory access speeds decrease
Solution Approach 1:
The patent implements dynamic voltage boosting by introducing a voltage boost circuit that temporarily increases the bit line voltage above the normal operating voltage during memory write operations. This dynamic voltage adjustment allows the memory circuit to operate at low voltages during normal standby periods (reducing power consumption) while achieving high-speed write operations when needed (improving memory access speed), thus resolving the contradiction between low power consumption and high speed operation
Solution Approach 2:
The patent changes the voltage parameter dynamically by using a voltage boost circuit that raises the bit line voltage to a higher level during write operations. This parameter change enables the system to overcome the speed limitations imposed by low operating voltages during critical operations, while maintaining low power consumption during non-operational periods
2Use of energy by stationary object
If operating voltage is decreased to reduce power consumption, then power consumption is reduced, but circuit speeds decrease
Solution Approach 1:
The voltage boost circuit provides dynamic voltage enhancement during write operations, allowing the memory circuit to maintain high productivity during critical operations while consuming minimal power during idle periods. The circuit transitions between low-voltage standby mode and high-voltage operational mode based on activity requirements
3Speed
If existing solutions are used to increase memory access speeds, then memory access speeds improve, but complexity and power consumption increase
Solution Approach 1:
The patent introduces a voltage boost circuit as an intermediary component that temporarily boosts the bit line voltage during write operations. This intermediary circuit enables high-speed memory access without requiring fundamental changes to the core memory array structure, thus improving speed while adding minimal complexity compared to more invasive architectural changes
Data Source
AI summary
A memory circuit includes a control circuit, a memory cell column, first and second bit lines coupled to the memory cell column, a write circuit coupled to a first end of each of the first and second bit lines, and a switching circuit including a first NAND gate including an input terminal coupled to the control circuit, an input terminal coupled to the first bit line, and a first output terminal, a first PMOS transistor coupled between a power supply node and the first bit line and including a gate coupled to the first output terminal, a second NAND gate including an input terminal coupled to the control circuit, an input terminal coupled to the second bit line, and a second output terminal, and a second PMOS transistor coupled between the power supply node and the second bit line and including a gate coupled to the second output terminal.