Bit Line Pillar Memory with Grouped Word Line Driving
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Solution Overview
Problem
Existing three-dimensional memory technologies face challenges in achieving high integration and reducing the area occupied by memory components, particularly the word line driving circuit, which is a significant contributor to memory size.
Innovation Solution
The memory design groups two or more word lines together and drives them simultaneously, reducing the number of word lines that need to be driven, thereby minimizing the area required for the word line driving circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines is increased to achieve higher memory capacity, then the memory capacity is improved, but the area occupied by the word line driving circuit increases
Solution Approach 1:
The patent merges multiple word lines into groups where two or more word lines are driven together as a unit. This combining approach reduces the total number of independent word line drivers needed, thereby decreasing the driving circuit area while maintaining the ability to access memory cells across multiple word lines, thus resolving the contradiction between memory capacity and driving circuit area.
2Quantity of substance
If more word lines are used to increase memory density, then the memory density is improved, but the device complexity increases
Solution Approach 1:
By grouping word lines and driving them together, the patent reduces the number of independent control signals and drivers required. This merging strategy simplifies the overall driving circuit architecture while still supporting high memory density through the use of multiple grouped word lines, effectively reducing device complexity.
3Device complexity
If the number of word lines is reduced to simplify the driving circuit, then the device complexity is reduced, but the memory capacity decreases
Solution Approach 1:
The patent makes each word line group serve multiple functions by enabling groups to be selected independently for different memory operations. Each grouped word line can function as an independent addressable unit, allowing the system to maintain high memory capacity with fewer, more versatile word line drivers, thus balancing complexity reduction with capacity preservation.
Data Source
AI summary
A memory may include a plurality of word lines formed of N layers, M word lines being arranged in each layer, among the plurality of word lines, where each of N and M is an integer of 2 or more; a plurality of bit line pillars; and a plurality of memory cells disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively. Among the plurality of word lines, two or more word lines of the plurality of word lines may be grouped and driven together.