3D Semiconductor Bit Line Positioning Under Memory Array
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Solution Overview
Problem
In three-dimensional (3D) semiconductor devices, the high density of bit lines in a block of memory array leads to significant signal interference between adjacent bit lines, which complicates data storage and operation reliability.
Innovation Solution
The bit lines and/or string selection lines are positioned under the memory array, allowing for reduced signal interference and simplifying the manufacturing process by relaxing the bit line pitch and reducing the need for deep contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are positioned above the memory array with high density, then storage capacity is increased, but signal interference between adjacent bit lines increases
Solution Approach 1:
The patent inverts the conventional bit line positioning by placing bit lines beneath the memory array instead of above it. This inversion allows bit lines to be positioned at a greater distance from each other, reducing capacitive coupling and signal interference while still achieving high storage capacity through vertical stacking of memory layers.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement where bit lines are densely packed in the same plane to a three-dimensional configuration where bit lines are positioned in a different vertical plane (beneath the memory array). This dimensional change increases the effective spacing between bit lines, reducing interference while maintaining high density through vertical stacking.
2Quantity of substance
If bit line pitch is reduced to increase density, then storage capacity is increased, but manufacturing precision requirements increase
Solution Approach 1:
By inverting the bit line position to beneath the memory array, the patent effectively increases the pitch between bit lines without reducing storage capacity. The vertical stacking of memory layers compensates for the reduced planar density, while the increased bit line pitch relaxes manufacturing precision requirements.
3Reliability
If deep contacts are used to connect bit lines, then electrical connectivity is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent inverts the contact structure by positioning bit lines beneath the memory array, which eliminates the need for deep vertical contacts through the memory stack. Instead, contacts can be formed more simply at the substrate level or through shorter vertical paths, reducing device complexity and manufacturing difficulty while maintaining electrical connectivity.
Data Source
AI summary
A 3D semiconductor device is provided, including several memory layers vertically stacked on a substrate, an upper selection layer formed on the memory layers, a lower selection layer formed above the substrate, several strings formed vertically to the memory layers and the substrate, several bit lines parallel to each other and disposed above the substrate. The memory layers are parallel to each other, and the strings are electrically connected to the upper selection layer and the lower selection layer. The bit lines are positioned under the memory layers.