Bit Line Selection Circuit for NAND Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND flash memory devices face challenges in achieving small size, high-capacity, fast access, and low power consumption due to the limitations of bit line selection circuits, particularly in the layout area and voltage handling capabilities of transistors.
Innovation Solution
The bit line selection circuit incorporates a first selection part with high-voltage transistors and a second selection part with low-voltage transistors, where the low-voltage transistors are formed with thinner gate oxide films and longer channel lengths, allowing for a smaller layout area and improved voltage handling, and are coupled in parallel to enhance driving ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage transistors with thicker gate oxide films and longer gate lengths are used in the bit line selection circuit, then voltage handling capability is improved, but layout area increases
Solution Approach 1:
The bit line selection circuit is divided into two separate parts: a first selection part using high-voltage transistors (BLC, BLS) for voltage handling, and a second selection part using low-voltage transistors (BLSe, BLSo, BIASe, BIASo) for bit line selection. This segmentation allows each part to use transistors optimized for its specific function, reducing the overall layout area while maintaining voltage handling capability.
Solution Approach 2:
Different regions of the circuit use different transistor types with different gate oxide thicknesses. The first selection part uses thick gate oxide transistors where high voltage is present, while the second selection part uses thin gate oxide transistors where only low voltage operates. This local differentiation optimizes both reliability and area efficiency.
2Area of stationary object
If low-voltage transistors with thinner gate oxide films and shorter gate lengths are used, then layout area is reduced, but voltage handling capability deteriorates
Solution Approach 1:
The circuit is segmented so that low-voltage transistors are used only in the second selection part where they operate at safe voltage levels, while high-voltage transistors handle the voltage-stressful first selection part. This allows area optimization without compromising overall voltage handling capability.
Solution Approach 2:
The high-voltage transistor BLS acts as an intermediary between the low-voltage second selection part and the high-voltage bit line. It isolates the low-voltage transistors from high voltage stress while enabling them to control high-voltage bit lines, allowing area-efficient low-voltage transistors to be used without sacrificing voltage handling capability.
3Reliability
If high-voltage transistors are used for both selection parts, then voltage handling is sufficient, but device size increases
Solution Approach 1:
The circuit implements local quality by using thick gate oxide transistors only where high voltage is present (first selection part), and thin gate oxide transistors where only low voltage operates (second selection part). This localized optimization reduces overall device size while maintaining voltage handling where needed.
Solution Approach 2:
The gate oxide thickness parameter is changed based on the voltage requirements of different circuit parts. Thick gate oxide is used in high-voltage regions for reliability, while thin gate oxide is used in low-voltage regions to minimize area, achieving an optimal balance between voltage handling and device size.
Data Source
AI summary
A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well.