Read-Only Memories TRIZ Cases

A semiconductor memory device uses control logic to switch between single and multi-sensing operations for verifying program states.

Segmented transistors in the bit line selection circuit reduce layout area while maintaining voltage handling capability for NAND flash memory.

A semiconductor memory block reconfigures defective multi-level cells into single-level mode to recover usable storage capacity.

A semiconductor memory device preserves unwritten data during power drops by transferring it to a variable resistance array, preventing NOR flash data loss.

An integrated circuit memory element receives commands and data sets within a single clock cycle to modify storage parameters.

Row-specific boost circuits elevate wordline and supply voltages to increase read current, preventing stability fails during scaled-down cell operations.

Auxiliary cells store program pulse counts to dynamically set the program start voltage, reducing verify operation time and preventing over-programming.

Dual reference levels compensate for threshold voltage shifts in non-volatile memory cells, preventing false data recognition during standing time.

Rebalancing mechanisms adjust threshold voltage states in twin-transistor memory cells, enabling multiple write cycles despite poor erase functions.

A resistive memory voltage equalizer synchronizes data and source lines to stabilize inactive states.

A 3D nonvolatile memory device applies distinct inhibit voltages to word lines above and below selected cells during programming operations.

A control circuit adjusts read pass voltages based on block programming status to optimize memory device power consumption.

Dynamic read voltage calculation minimizes bit error rates caused by overlapping voltage distributions in non-volatile semiconductor memory devices.

A semiconductor memory programming method applies a first program voltage followed by a rising step pulse to control threshold voltage distribution.

Per-cell quality measurement enables even load distribution across EEPROM segments, extending device lifetime under high-stress write conditions.

Applying audit verify voltages to erased wordlines detects threshold shifts, preventing read disturb errors and extending block lifetime.

Compensates for back pattern dependency and program disturbances by detecting programmed or erased sub-block states to adjust read voltage.

Controllers optimize power consumption and speed by selecting between in-place writes and pre-set operations based on expected data changes.

Diode-connected PFET feedback balances margining current across threshold voltage shifts to resolve true-complement asymmetry in charge-trap memory.

A clock signal processor modifies duty cycles using a switch point calculator and multiplexer to generate accurate timing signals.

Determining least erased and programmed levels to set read reference voltage for non-volatile memory cells.

Checkpoint states minimize verify tests to shorten program time while maintaining threshold voltage precision.

Alternating bit line coupling eliminates source connections in NAND arrays, reducing power consumption and fabrication complexity.

A hybrid hard disk drive writes test data alongside user data to detect incipient charge leakage in NAND flash memory cells.

Adaptive erase and read verification adjusts parameters based on unwritten space in NAND blocks, preventing false verify errors.

Segmenting word lines into even and odd groups allows the driver to apply different voltages, reducing power consumption while maintaining erasing reliability.

Programming dummy cells via hot carrier injection or Fowler-Nordheim tunneling suppresses leakage currents in vertically stacked memory arrays.

A flash memory controller monitors voltage distribution shifts to trigger block refresh operations.

A 3D NAND storage device applies distinct erase and prohibition voltages to separate bit lines for targeted data erasure.

Periodic force writes refresh cells between normal cleans, reducing wear while maintaining cleaning effectiveness.

A nonvolatile memory device applies a turn-on voltage to word lines via the memory controller.

Reversible hydrogen insertion into semiconducting metal oxide layers achieves high endurance and low operational power through shallow donor effects.

Applying precharge voltage to the source line and first source select line reduces capacitive coupling disturbances during program operations.

Segmented even and odd pass transistors isolate selected memory cells from adjacent unselected lines, eliminating capacitive coupling errors.

Reducing unselected wordline bias during multistrobe sensing decreases read disturb and extends NAND flash operational lifespan.

A shared pump circuit generates gate voltages for multiple word lines in nonvolatile semiconductor memory arrays.

A controller dynamically adjusts the start time of forced refresh operations for non-volatile memory blocks based on workload conditions.

Pre-programming pulses narrow threshold voltage distributions to reduce electrical coupling effects in nonvolatile memory devices.

A semiconductor memory device uses a writing transistor with extremely low leakage current to store data in a matrix configuration.

Selective data pattern write scrub reduces media degradation by tracking scrub cycles and rewriting only vulnerable memory cells, improving read accuracy.

A method selects a subset of half reference values from memory cells to determine a reliable reference value.

Iterative read retry operations adjust voltage levels to retrieve data, resolving cell distribution migration that degrades read reliability.

Relocating biasing logic to an external controller reduces die size and design cycle time by removing internal combinational circuitry.

A 2T AND flash memory array uses independent bit line voltage control to manage memory segment selection.

Applying distinct program permission voltages to grouped bit lines reduces cell speed deviation and minimizes verify operations.

A memory device detects fail cells using over-bit verify voltage during programming operations.

Applying counter-transitioning waveforms to neighboring word lines reduces capacitive coupling during non-volatile memory programming operations.

A two-stage sense amplifier separates primary voltage sensing from secondary logic amplification to enable high-speed data reading.