Semiconductor Readout Circuit Using Dual Reference Levels
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Solution Overview
Problem
Non-volatile memory cells exhibit unusual behavior during standing time, leading to false data recognition due to charge loss or gain, particularly in SONOS type flash memory, where threshold voltages change, causing misinterpretation of data 0 and data 1.
Innovation Solution
A semiconductor device with a readout circuit that generates and uses two reference levels: one based on a dynamic reference cell and an external reference cell, allowing for accurate data reading by comparing the memory cell's level with these references, thereby preventing false recognition of memory cell data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single reference level is used for reading out memory cell data, then the readout process is simple, but false recognition occurs when memory cells exhibit unusual behavior during standing time
Solution Approach 1:
The single reference level is segmented into multiple reference levels (first reference level and second reference level), each serving different reading purposes. This segmentation allows the system to handle different memory cell states separately, improving recognition accuracy while maintaining operational simplicity through structured multi-level comparison.
Solution Approach 2:
The reference level parameter is changed from a single fixed value to multiple adjustable reference levels. By dynamically selecting and adjusting reference levels based on memory cell behavior during standing time, the system adapts to threshold voltage changes and prevents false recognition while keeping the readout process manageable.
2Reliability
If dynamic reference cells with the same writing and erasing history are used, then charge loss and charge gain effects are compensated, but memory cells exhibiting unusual behavior still cause false recognition
Solution Approach 1:
The reference cell system transitions from static to dynamic by introducing multiple reference levels that can be selectively activated. The first reference level uses dynamic reference cells for normal operation, while the second reference level provides an alternative reference for memory cells exhibiting unusual behavior, enabling adaptive compensation and precise reading throughout standing time.
Solution Approach 2:
The system performs preliminary classification of memory cells by testing their behavior during standing time before final data reading. This preliminary action identifies memory cells with unusual behavior, allowing the system to switch between different reference levels appropriately and ensure accurate reading without false recognition.
Data Source
AI summary
The present invention is directed to a semiconductor device having a non-volatile memory cell 18, and a readout circuit 102 which reads out data of the memory cell 18 DATA using a first data DATA1 obtained by sensing a first reference level REF1 for reading out the data of the memory cell 18 and a level of the memory cell 18 CORE and using a second data DATA2 obtained by sensing a second reference level REF2 for reading out the data of the memory cell 18 and the level of the memory cell 18 CORE, and to a controlling method for the same.