Semiconductor Memory Block Redesign for Defective Cell Recovery
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Solution Overview
Problem
Semiconductor memory devices face issues with defective cell strings exceeding the limited number of redundancy cell strings, leading to unusable memory blocks and reduced data storage capacity.
Innovation Solution
A semiconductor memory device and method that determine whether a memory block with defective multi-level cells can operate as single level cells, allowing such blocks to be used as single level cell blocks by designating them as such, thereby extending their usability and increasing data storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-level cell program operations are performed with increased program voltage, then program capability is improved, but the number of defective cells increases due to process variations
Solution Approach 1:
The patent implements dynamic voltage adjustment during the program operation. The control circuit dynamically increases the program voltage from an initial voltage to a higher voltage based on the number of times the program operation is performed. This dynamic voltage adjustment allows the system to adapt to cell programming characteristics over time, improving program capability while managing the risk of creating defective cells through excessive voltage application.
Solution Approach 2:
The patent changes the voltage parameter during the program operation. Specifically, the program voltage is increased by a predetermined voltage amount each time the program operation is repeated. This parameter change enables the system to overcome varying threshold voltage distributions of memory cells and achieve reliable programming while monitoring for defective cells that may result from the increased voltage stress.
2Reliability
If redundancy cell strings are used to replace defective cell strings, then reliability is improved, but the number of usable memory blocks decreases due to limited redundancy
Solution Approach 1:
The patent changes the operational parameter of memory blocks from multi-level cell mode to single-level cell mode. When a memory block is determined to have excessive defective cells for multi-level operation, the control circuit designates it as a single-level cell block. This parameter change allows the memory block to remain usable with a different cell configuration, thereby increasing the total number of usable memory blocks while maintaining reliability through the use of redundancy cell strings for critical defects.
3Reliability
If memory blocks with excessive defective cells are discarded as bad blocks, then reliability of remaining blocks is maintained, but data storage capacity is reduced
Solution Approach 1:
The patent changes the operational mode parameter of potentially defective memory blocks from multi-level cell operation to single-level cell operation. Instead of discarding memory blocks with excessive defective cells, the control circuit designates them as single-level cell blocks where the program voltage is not increased beyond the initial voltage. This parameter change enables these blocks to contribute to the total storage capacity while maintaining reliability by avoiding the voltage stress that would create additional defective cells in multi-level mode.
Solution Approach 2:
The patent converts the harm of having defective cells in multi-level mode into a benefit by redesignating those same memory blocks for single-level cell operation. Memory blocks that would be discarded as bad blocks in traditional approaches are instead repurposed as single-level cell blocks, transforming what would be wasted capacity into usable storage. This approach maintains reliability by avoiding further voltage-induced defects while maximizing the quantity of usable memory.
Data Source
AI summary
A semiconductor memory device includes memory blocks each including a plurality of groups of memory cells programmable in multiple levels and a control circuit configured to make a determination of whether a specific memory block treated a bad block, from among the memory blocks, is programmable in a single level and to control the specific memory block according to a result of the determination so that the specific memory block is usable as a single level cell block.