External Controller Biasing for Memory Die Size Reduction
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Solution Overview
Problem
Existing memory devices face challenges in efficiently controlling access line biasing schemes, leading to increased design cycle time, die size, and reduced flexibility and functionality due to the implementation of multiple biasing schemes using combinational logic within the device.
Innovation Solution
Shifting the selection of word line dependent biasing schemes and corresponding bias conditions to a controller external to the memory device, allowing for flexible selection and adjustment of biasing schemes without modifying internal hardware, thereby reducing the need for complex combinational logic and increasing design efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple biasing schemes are implemented using combinational logic within the memory device, then the memory device can provide various access line dependent biasing schemes, but the design cycle time increases and die size increases
Solution Approach 1:
The patent extracts the biasing scheme selection logic from the memory device itself and relocates it to an external controller. This removes the combinational logic circuitry from the memory device die, thereby reducing die size while maintaining the capability to implement multiple access line dependent biasing schemes through the external controller's programming and control mechanisms.
2Adaptability or versatility
If multiple biasing schemes are implemented using combinational logic within the memory device, then the memory device can provide various access line dependent biasing schemes, but the design cycle time increases
Solution Approach 1:
By extracting the complex combinational logic for biasing scheme selection from the memory device and placing it in an external controller, the patent simplifies the memory device design. This reduction in internal logic complexity directly decreases design cycle time while the external controller maintains adaptability through software or configuration-based biasing scheme selection.
3Adaptability or versatility
If multiple biasing schemes are implemented using combinational logic within the memory device, then the memory device can provide various access line dependent biasing schemes, but the hardware complexity increases
Solution Approach 1:
The patent removes the combinational logic hardware from the memory device and relocates the biasing scheme selection functionality to an external controller. This extraction eliminates the hardware complexity within the memory device while preserving the versatility of multiple biasing schemes through the external controller's programmable or configurable logic.
4Reliability
If access operations are performed with precise control over access lines, then program disturb and read disturb are reduced, but the control complexity increases
Solution Approach 1:
The patent introduces an external controller as an intermediary between the memory device and the biasing scheme selection process. This intermediary handles the complexity of selecting and applying the appropriate biasing scheme based on the target access line position, thereby achieving precise control that reduces program disturb and read disturb while keeping the memory device itself relatively simple.
Data Source
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AI summary
The present disclosure includes methods, devices, and systems for access line biasing. One embodiment includes selecting, using a controller external to the memory device, a particular access line dependent biasing scheme and corresponding bias conditions for use in performing an access operation on an array of memory cells of the memory device, and performing the access operation using the selected particular access line dependent biasing scheme and corresponding bias conditions. In one or more embodiments, the selected particular access line dependent biasing scheme and corresponding bias conditions is selected by the controller external to the memory device based, at least partially, on a target access line of the array.