Bit-Addressable PCM Writes for Neural Network Data Updates
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Solution Overview
Problem
Conventional NAND arrays do not allow for in-place bit-addressable writes, which limits the efficiency of updating data, especially in deep learning applications where frequent and precise changes are necessary, whereas phase-change memory (PCM) arrays enable bit-addressable writes but require efficient update strategies to manage power consumption and speed.
Innovation Solution
The implementation of a method that determines the amount of change in data to be updated, deciding between an In-place Write (IPW) and an In-place Write with Pre-set (IPWwP) within the PCM array, where IPWwP pre-sets all bits to a first state before updating specific bits using fast RESET pulses, optimizing power consumption and speed based on the number of bits to be changed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If in-place bit-addressable writes are performed in PCM arrays, then data update efficiency is improved, but power consumption increases when updating large amounts of data
Solution Approach 1:
The patent applies preliminary action by pre-setting memory cells to a specific state (e.g., resistance state corresponding to logic '1') before performing bit-addressable writes. This pre-conditioning of the memory state allows subsequent write operations to be more efficient and consume less power, as the actual data updates only need to change bits from the pre-set state to their target state, rather than handling all possible state transitions.
2Speed
If in-place bit-addressable writes are performed in PCM arrays, then data update speed is improved, but power consumption increases for frequent updates
Solution Approach 1:
The patent pre-conditions memory cells by setting them to a specific resistance state before update operations. This preliminary action enables faster subsequent write operations while reducing power consumption, as the pre-set state optimizes the conditions for rapid state changes during actual data updates.
Solution Approach 2:
The patent changes the resistance state parameter of memory cells as a pre-conditioning step before performing bit-addressable writes. By adjusting this physical parameter (resistance state) in advance, the system optimizes both the speed and power efficiency of subsequent write operations, allowing rapid state transitions with reduced energy expenditure.
3Use of energy by moving object
If conventional NAND arrays are used, then power consumption is reduced, but in-place bit-addressable writes are not allowed
Solution Approach 1:
The patent utilizes the ability of PCM arrays to change resistance states as a fundamental parameter, enabling in-place bit-addressable writes. By leveraging this parameter change capability, the system achieves both low power consumption (comparable to NAND) and the operational flexibility of bit-level updates, resolving the contradiction between power efficiency and update capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency of data updates in PCM arrays by reducing power consumption and latency, particularly in deep learning applications, by selectively using IPW or IPWwP based on the amount of data change, thereby improving the performance and reliability of neural network computations.
Implementation Method 1
phase-change memory (PCM) arrays, which allows for in-place bit-addressable writes (read-modify-writes)
Data Source
AI summary
Methods and apparatus are disclosed for managing the storage of dynamic neural network data within bit-addressable memory devices, such phase change memory (PCM) arrays or other storage class memory (SCM) arrays. In some examples, a storage controller determines an expected amount of change within data to be updated. If the amount is below a threshold, an In-place Write is performed using bit-addressable writes via individual SET and RESET pulses. Otherwise, a modify version of an In-place Write is performed where a SET pulse is applied to preset a portion of memory to a SET state so that individual bit-addressable writes then may be performed using only RESET pulses to encode the updated data. In other examples, a storage controller separately manages static and dynamic neural network data by storing the static data in a NAND-based memory array and instead storing the dynamic data in a SCM array.