3D Flash Memory Read Voltage Adjustment for Sub-Block Disturbance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional (3D) flash memory devices face challenges in reliability and performance due to back pattern dependency and program disturbances, which affect read margins and data integrity.
Innovation Solution
A method is introduced to adjust the read bias of selected memory cells in nonvolatile memory devices based on the state information of unselected sub-blocks, compensating for variations in channel resistance and program disturbances by detecting the number of programmed or erased sub-blocks and adjusting the read voltage and sensing time accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read voltage is adjusted based on sub-block state information, then read margin and data integrity are improved, but device complexity and control overhead increase
Solution Approach 1:
The memory controller pre-detects and stores state information of unselected sub-blocks (programmed or erased state) before performing read operations. This preliminary detection allows the controller to anticipate and compensate for back pattern dependency effects, adjusting read voltage proactively rather than reactively, thereby improving read margin while managing complexity through advance preparation
Solution Approach 2:
The system implements a feedback mechanism where the detected state information of unselected sub-blocks is fed back to dynamically adjust the read voltage applied to selected memory cells. This closed-loop control compensates for program disturbances and back pattern dependency in real-time, improving data integrity while the feedback is managed through efficient state tracking algorithms
Solution Approach 3:
The read voltage parameter is dynamically changed based on the detected state information of unselected sub-blocks. By adjusting the read voltage level according to whether neighboring sub-blocks are programmed or erased, the system compensates for threshold voltage shifts and maintains optimal read margins without requiring fundamental changes to the memory architecture
2Reliability
If state detection and voltage adjustment are implemented, then data integrity is improved, but operation time and processing overhead increase
Solution Approach 1:
State information of unselected sub-blocks is detected and stored in advance during erase or program operations, before read operations are performed. This preliminary detection eliminates the need for time-consuming state analysis during actual read operations, reducing operation time while maintaining data integrity through pre-computed compensation values
Solution Approach 2:
The system performs state detection selectively for unselected sub-blocks that are likely to affect the read operation, rather than analyzing the entire memory block. This partial action approach reduces processing overhead and operation time while still providing sufficient information for accurate read voltage adjustment and data integrity maintenance
Data Source
AI summary
A method of operating a nonvolatile memory device configured to erase a memory block in sub-block units comprises detecting state information of unselected sub-blocks associated with a selected sub-block comprising selected memory cells, adjusting a read bias of the selected memory cells based on the state information, and reading data from the selected memory cells according to the adjusted read bias. The state information indicates a number of the unselected sub-blocks having a programmed state or an erased state.