Semiconductor Memory Verification Using Adaptive Sensing
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing program verification time, particularly due to inaccuracies in sensing threshold voltages during the verification process, especially in initial program operations where source bouncing phenomena occur.
Innovation Solution
The semiconductor memory device employs a control logic that selectively performs either a single sensing operation or a multi sensing operation based on the number of applied program pulses or verification operations, using a page buffer to sense threshold voltages and differentiate between erase and program cells, thereby optimizing the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single sensing operation is performed during verification, then the verification time is reduced, but the sensing accuracy deteriorates due to source bouncing phenomena in initial program operations
Solution Approach 1:
The sensing operation mode is dynamically changed based on the program pulse count. The control logic selectively switches between single sensing operation and multi sensing operation according to whether the current program pulse count is less than or equal to a reference value, optimizing both speed and accuracy at different stages
Solution Approach 2:
The sensing operation parameters are changed based on program progression. When the program pulse count exceeds the reference value, the system transitions from multi sensing operation (higher accuracy) to single sensing operation (faster), adapting the sensing parameters to the current program state
2Measurement precision
If a multi sensing operation is performed during verification, then the sensing accuracy is improved, but the verification time increases
Solution Approach 1:
The sensing operation mode is dynamically adjusted based on program pulse count. The control logic selectively performs multi sensing operation only when needed (in initial stages with program pulse count ≤ reference value), and switches to single sensing operation in later stages, optimizing the balance between accuracy and time
Solution Approach 2:
The verification process is segmented into different stages based on program pulse count. The first stage (program pulse count ≤ reference value) uses multi sensing operation for accuracy, while the second stage (program pulse count > reference value) uses single sensing operation for speed, dividing the verification process into distinct phases
Data Source
AI summary
A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device may include a memory cell array including a plurality of memory cells, and a peripheral circuit configured to perform a program pulse applying operation and a verification operation on the memory cell array. The semiconductor memory device may include a control logic configured to control the peripheral circuit to selectively perform a single sensing operation or a multi sensing operation during the verification operation.