Semiconductor Memory Device Bit Line Grouping for Program Speed Uniformity
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Solution Overview
Problem
Semiconductor memory devices face limitations in operating speed due to variations in program speed between memory cells, which affect the efficiency of programming operations.
Innovation Solution
The solution involves grouping bit lines based on program speeds and applying different program permission voltages to bit lines coupled to memory cells, allowing for adjusted voltages to be applied during blind programming operations to reduce deviations in program speed and enhance overall programming efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If uniform program permission voltage is applied to all bit lines, then circuit design is simplified, but program speed deviation between memory cells increases
Solution Approach 1:
The patent applies different program permission voltages to different bit line groups based on their specific characteristics. Bit lines are divided into multiple groups, and each group receives a customized voltage level to compensate for position-dependent program speed variations, achieving local optimization rather than uniform treatment
Solution Approach 2:
The patent changes the voltage parameter of bit lines by applying different program permission voltages to different bit line groups. This parameter adjustment compensates for program speed deviations caused by physical position differences, thereby improving program speed uniformity across all memory cells
2Manufacturing precision
If verify operations are performed frequently, then program accuracy is improved, but overall program speed decreases
Solution Approach 1:
The patent applies different program permission voltages in advance to bit line groups before the actual programming operation. This preliminary voltage adjustment ensures that memory cells across different positions achieve more uniform program speeds, reducing the need for frequent verify operations and thereby improving overall program efficiency
Data Source
AI summary
A semiconductor memory device may include a memory cell array, a peripheral circuit and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a program operation on a selected memory block among the memory blocks. The control logic may control the program operation of the peripheral circuit. The selected memory block may be coupled with a plurality of bit lines, and the bit lines may be grouped into a first bit line group and a second bit line group based on programming speeds of memory cells coupled to the bit lines that are grouped into the first and second bit line groups. During a blind program operation of the selected memory block, the control logic may control the peripheral circuit to apply different program permission voltages to bit lines of at least two bit line groups.