Read Disturb Audit in Open NAND Memory Blocks
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Solution Overview
Problem
NAND flash memory reliability degrades due to read disturb errors, where read operations on one row of flash cells impact threshold voltages of unread cells, leading to incorrect logical states and errors, especially in scaled-down memory systems with uneven read distributions.
Innovation Solution
Implementing audit techniques that apply specific voltages to erased wordlines in open memory blocks to accurately assess read disturb levels, allowing for more reliable detection and prevention of errors, including single wordline issues and varying block conditions, without increasing audit time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read operations are performed on one row of flash cells, then data access is enabled, but threshold voltages of unread cells in different rows are impacted causing read disturb errors
Solution Approach 1:
The patent applies preliminary action by performing an audit verify operation on erased wordlines before normal read operations. This preliminary detection identifies cells that have already experienced threshold voltage shifts due to read disturb, allowing the system to prevent erroneous reads and mark affected blocks for erasure before errors propagate
Solution Approach 2:
The patent implements feedback through the audit verify mechanism that continuously monitors erased wordlines for threshold voltage changes. When read disturb causes threshold shifts, the audit verify detects these changes and feeds back to the memory controller, which then adjusts operation by avoiding reads on affected wordlines or erasing the block to restore reliability
2Quantity of substance
If memory is scaled down and more bits are programmed per cell, then storage capacity increases, but read disturb effects are amplified causing more errors
Solution Approach 1:
The audit verify operation serves as a preliminary detection mechanism that identifies read disturb affected cells before they cause errors. This is particularly important for scaled memory where read disturb effects are amplified, allowing the system to proactively detect and handle vulnerable cells in high-density configurations
Solution Approach 2:
The patent changes the operational parameters by introducing audit verify voltages that are specifically tailored to detect threshold voltage shifts in erased cells. The method uses verify read operations with appropriate voltage levels to detect subtle threshold changes that occur in scaled memory devices, enabling detection even when multiple bits are programmed per cell
3Measurement precision
If audit techniques are applied to all memory blocks, then detection accuracy improves, but audit time increases
Solution Approach 1:
The patent applies local quality by focusing the audit verify operation specifically on erased wordlines rather than all wordlines in a block. Since read disturb primarily affects erased cells, this localized approach achieves high detection accuracy for the vulnerable population while minimizing the time penalty by excluding already-programmed wordlines from the audit process
4Ease of operation
If conventional read disturb detection is used, then simple operation is maintained, but single wordline issues and varying block conditions cannot be detected
Solution Approach 1:
The patent segments the memory block into programmed wordlines and erased wordlines, applying different operations to each segment. The audit verify is specifically applied to erased wordlines where read disturb occurs, while programmed wordlines continue normal operation. This segmentation enables precise detection of single wordline issues and varying block conditions without complicating the overall operation
Data Source
AI summary
Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count representing a number of non-conductive bitline(s) is determined and compared to a threshold value to determine whether to continue or discontinue block operation. In an audit verify and audit gap technique, the erased wordlines are divided into disjoint first and second groups, and an audit verify voltage and a non-verify voltage are alternatively applied to the groups in different audit verify stages.