Column Decoder with Segmented Bit Lines for Capacitive Coupling
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Solution Overview
Problem
Conventional memory devices experience significant capacitive coupling effects between adjacent memory cells due to parasitic capacitances, leading to operation errors and reduced reliability as the device size decreases, causing unintended current flows through unselected local bit lines.
Innovation Solution
The memory device incorporates a column decoder with even and odd pass transistors, where each local bit line is selectively coupled to a separate global bit line, allowing for the disabling of unselected transistors and grounding of adjacent local bit lines to mitigate capacitive coupling, thereby reducing mutual coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the memory device size is reduced to increase integration density, then the manufacturing precision and area utilization are improved, but the capacitive coupling effect between adjacent memory cells increases causing operation errors
Solution Approach 1:
The patent divides the global bit line system into separate even and odd global bit lines (GBL0, GBL1), with corresponding even and odd pass transistors. This segmentation allows independent control of adjacent bit lines, enabling the selection transistor to be turned off while the adjacent bit line can be independently grounded through its dedicated pass transistor, thereby eliminating capacitive coupling effects while maintaining high integration density
Solution Approach 2:
The patent introduces separate even and odd pass transistors as intermediary control elements between the local bit lines and global bit lines. These intermediary transistors enable independent control and grounding of adjacent bit lines, acting as mediators to prevent direct capacitive coupling between selected and unselected memory cells, thus improving operation reliability in scaled-down devices
2Device complexity
If adjacent local bit lines are kept floating during operation, then the device complexity is reduced, but capacitive coupling induces unintended current flows through unselected memory cells
Solution Approach 1:
The patent segments the bit line control into even and odd groups with separate pass transistors and global bit lines. This segmentation enables the unselected adjacent bit line to be actively grounded through its dedicated pass transistor rather than left floating, effectively preventing capacitive coupling currents while adding minimal control complexity through the use of separate even and odd selection lines
Solution Approach 2:
The patent applies preliminary anti-action by proactively grounding the unselected adjacent local bit line through its dedicated pass transistor before capacitive coupling can induce harmful currents. The separate even and odd pass transistors enable this preventive grounding action, counteracting the potential harmful effect of capacitive coupling before it can cause operation errors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively eliminates capacitive coupling between adjacent memory cells, enhancing the reliability and reducing error rates during read and program operations by ensuring that selected local bit lines are isolated from adjacent lines, which are grounded.
Implementation Method 1
each of the even pass transistors has a control terminal coupled to a respective one of a plurality of even selection lines, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to an even global bit line
Implementation Method 2
when one of the even pass transistors is selected and enabled, disabling the other unselected even pass transistors, enabling all of the odd pass transistors, and pulling down all of the odd local bit lines to a ground voltage by the odd global bit line
Data Source
AI summary
A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors and a plurality of odd pass transistors. Each of the even pass transistors has a, control terminal coupled to a respective one of a plurality of even selection lines, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to an even global bit line. Each of the odd pass transistors has a control terminal coupled to a respective one of a plurality of odd selection lines, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to an odd global bit line.