3D NAND Selective Erasure via Bit Line Voltage Control
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Solution Overview
Problem
Current storage devices, such as flash memory, erase data in units of blocks, which are larger than cells, limiting the size of controllable units for erasure.
Innovation Solution
A storage device with a 3D nonvolatile memory system where each memory block consists of cell strings connected to a common source line and bit lines, allowing for selective erasure of data on one bit line while preserving data on another by applying different voltages and floating the common source line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If erasing is performed in units of blocks, then the erasure operation is simple and reliable, but the controllable unit size is large causing unnecessary data loss
Solution Approach 1:
The patent divides the memory block into smaller erasure units by introducing bit line groups and controlling erasure at the bit line group level rather than the entire block level. This segmentation allows selective erasure of only the necessary portions of memory, improving erasure precision while minimizing data loss in preserved regions.
Solution Approach 2:
The patent applies different voltage conditions to different bit line groups within the same memory block. By applying erase voltages to selected bit lines while applying prohibition voltages to others, the system creates local erasure zones with different qualities, enabling precise control over which data is erased and which is preserved.
2Ease of operation
If erasing is performed in units of blocks, then the control mechanism is simple, but the erasure granularity is coarse
Solution Approach 1:
The memory block is segmented into multiple bit line groups that can be independently controlled for erasure operations. This segmentation enables finer granularity control while maintaining a relatively simple control structure through the use of prohibition voltages applied to unselected groups.
Solution Approach 2:
The patent changes the voltage parameters applied to different bit lines during erasure operations. By varying voltage levels (erase voltages versus prohibition voltages) across different bit line groups, the system achieves fine-grained control over erasure granularity without significantly complicating the control mechanism.
3Manufacturing precision
If different voltages are applied to different bit lines for selective erasure, then erasure precision is improved, but the voltage control complexity increases
Solution Approach 1:
Different voltage conditions are applied to different bit line groups to achieve selective erasure. Erase voltages are applied to bit lines requiring erasure while prohibition voltages are applied to bit lines requiring data preservation, creating locally differentiated voltage zones that enable precise selective erasure.
Solution Approach 2:
Instead of actively controlling which bit lines to erase through complex enable signals, the patent uses prohibition voltages to protect bit lines that should retain data, while allowing default erasure to proceed on unprotected bit lines. This inverted approach simplifies the control logic by focusing on preservation rather than selection.
4Loss of information
If the common source line is floated during erasure, then data preservation in unselected cell strings is achieved, but the control mechanism becomes more complex
Solution Approach 1:
The common source line acts as an intermediary element that, when floated, creates an electrical condition that prevents charge tunneling in unselected cell strings. This floating state serves as a mediator that passively protects data in bit line groups where prohibition voltages are applied, enabling data preservation without requiring active control of each individual cell string.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables erasure of data in units smaller than blocks, improving control over erasure operations and reducing unnecessary data loss, while maintaining preserved data without the need for rewriting.
Implementation Method 1
apply an erase voltage to a first bit line of the plurality of bit lines of at least one memory block
Implementation Method 2
apply an erase prohibition voltage to a second bit line of the plurality of bit lines, the erase prohibition voltage having a voltage level lower than a voltage level of the erase voltage
Implementation Method 3
float the common source line, the floating the common source line causing an erasure of data stored in at least one first memory cell included in at least one first cell string connected to the first bit line
Data Source
AI summary
A storage device capable of performing erase operations in units smaller than blocks may include nonvolatile memory, and processing circuitry configured to, apply an erase voltage to a first bit line of the plurality of bit lines of at least one memory block of the plurality of memory blocks, apply an erase prohibition voltage to a second bit line of the plurality of bit lines, the erase prohibition voltage having a voltage level lower than a voltage level of the erase voltage, and float the common source line to cause an erasure of data stored in at least one first memory cell included in at least one first cell string connected to the first bit line by floating the common source line, and preserve data stored in at least one second memory cell included in at least one second cell string connected to the second bit line.