Variable Read Voltage Optimization for Multi-Bit Memory Error Reduction
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Solution Overview
Problem
Existing non-volatile memory devices, such as flash EEPROM, face challenges in minimizing read data errors due to overlapping voltage states, which can lead to incorrect data retrieval, and current methods do not effectively optimize read voltage settings to reduce these errors.
Innovation Solution
A method is introduced to calculate and set an optimal read voltage level by determining the minimal read data error probability based on variable read voltage levels, using techniques such as averaging and variance calculations, and offset compensation to distinguish between adjacent voltage states, thereby minimizing bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed read voltage is used for multi-bit memory cells, then the device structure is simple, but read data errors occur due to overlapping voltage states
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed read voltage to a variable read voltage that is dynamically adjusted based on detected voltage distributions. The system measures voltage distributions during read operations and adapts the read voltage accordingly, allowing the memory device to handle overlapping voltage states in multi-bit cells without requiring complex hardware modifications.
Solution Approach 2:
The patent implements parameter changes by modifying the read voltage parameter based on measured voltage distributions. The system calculates optimal read voltage values by analyzing the detected voltage distributions and adjusting the read voltage parameter to minimize read errors, thereby improving reliability without adding significant device complexity.
2Quantity of substance
If multiple voltage states are stored in memory cells to increase density, then storage capacity improves, but voltage state overlap causes read errors
Solution Approach 1:
The patent applies feedback by implementing a closed-loop system that measures voltage distributions during read operations and uses this information to adjust read voltage settings. The system continuously monitors voltage distributions and adapts read parameters accordingly, enabling accurate reading of multiple voltage states without sacrificing reliability due to state overlap.
Solution Approach 2:
The patent replaces traditional mechanical or fixed voltage reading mechanisms with an electronic measurement and adjustment system. Instead of using fixed voltage thresholds, the system employs electronic voltage distribution measurement and computational analysis to determine optimal read voltages, substituting rigid mechanical reading approaches with flexible electronic adaptation.
3Reliability
If conventional read voltage methods are used, then the method is simple, but read data errors cannot be minimized
Solution Approach 1:
The patent implements preliminary action by performing voltage distribution measurements and optimal read voltage calculation before actual data read operations. The system pre-characterizes voltage distributions and determines optimal read voltages in advance, allowing subsequent read operations to use these pre-calculated values without requiring complex real-time computation during data reading.
Solution Approach 2:
The patent applies copying by creating a model or representation of voltage distributions through measurement and analysis. The system copies voltage distribution characteristics into a usable format that can be processed to determine optimal read voltages, allowing the complex physical voltage states to be represented and manipulated in a simplified computational manner.
Data Source
AI summary
A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states.