Twin-Cell Memory Rebalancing for Multiple Writes
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Solution Overview
Problem
Twin-transistor memory cells face read failures due to initial VT offset and partial erasing conditions, especially when the erase function is poor or non-existent, limiting multiple write cycles and data storage reliability.
Innovation Solution
A rebalancing mechanism is applied to bring the true and complement sides of the twin-transistor memory cell back to equilibrium by writing the inverse of the previous data, enabling multiple write cycles even when the erase function is ineffective, by modifying the threshold voltage states of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If twin-transistor memory cells are used for high density storage, then storage capacity is improved, but read failures occur due to initial VT offset and partial erasing conditions
Solution Approach 1:
The patent applies preliminary action by performing a rebalancing write operation before the actual data write. This rebalancing step pre-adjusts the threshold voltages of the true and complement transistors to eliminate initial VT offset, ensuring that the memory cell starts in a balanced state that prevents read failures during subsequent write and read operations
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the threshold voltage (VT) parameters of the transistors through controlled charge injection. The system changes the VT parameters of both true and complement transistors during the rebalancing process to maintain equilibrium, and then changes only the required transistor's VT during the actual write operation, enabling reliable multiple write cycles
2Device complexity
If erase function is poor or non-existent, then device complexity is reduced, but multiple write cycles are limited
Solution Approach 1:
The patent extracts the erase function from the memory cell operation by separating the rebalancing function into a distinct preliminary write operation. Instead of relying on a dedicated erase mechanism, the system uses a specialized write operation that achieves the equivalent effect of erasing by balancing both transistors to a reference state, thereby enabling multiple write cycles without requiring a complex erase function
Solution Approach 2:
The patent applies universality by making the write circuit perform multiple functions: it can write actual data, perform rebalancing operations, and enable multiple write cycles without a dedicated erase function. The same write circuitry is used for both data programming and threshold voltage balancing, simplifying the overall device architecture while maintaining multiple write capability
3Device complexity
If threshold voltage states are not rebalanced, then device complexity is reduced, but sensing accuracy deteriorates
Solution Approach 1:
The patent applies preliminary action by performing the rebalancing write operation before the actual data write operation. This preliminary step ensures that the threshold voltages of both true and complement transistors are equalized, creating a balanced starting point that maximizes sensing accuracy for subsequent read operations without adding complexity during the read process itself
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach extends the useful lifetime of twin-cell flash memory by allowing continuous data storage variation over a broad range, ensuring accurate sensing and reliable multiple write cycles, even in conditions where the erase function is incomplete.
Implementation Method 1
its Vt of the transistor (i.e. 15B or 15A) of the target memory cell 11 gets shifted from its nominal value (0.25V ̃0.3V) to a higher value (e.g. ̃0.45 to 0.5V) due to BTI (Bias temperature instability) and HCl (hot carrier injection) effects
Implementation Method 2
its Vt of the transistor (i.e. 15B or 15A) of the target memory cell 11 gets shifted from its nominal value (0.25V ̃0.3V) to a higher value (e.g. ̃0.45 to 0.5V) due to BTI (Bias temperature instability) and HCl (hot carrier injection) effects
Data Source
AI summary
A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.