Semiconductor Memory Device with Low Leakage Transistor for High Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices face limitations in data retention time, integration density, and the number of write cycles, with DRAM losing data when power is off, SRAM having low integration, and FGNVMs requiring high voltage for writing and suffering from interference between memory cells.
Innovation Solution
A semiconductor memory device structure utilizing a writing transistor with low leakage current, a reading transistor for high-speed operation, and a capacitor with specific dielectric materials, arranged in a matrix with optimized wiring configurations to reduce voltage requirements and increase integration density, allowing for long data retention and high write cycle counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a conventional FGNVM structure is used to achieve non-volatile storage, then data retention time is improved (one year or longer), but the number of write cycles is limited (one hundred thousand or less) and high voltage is required causing gate insulating film deterioration
Solution Approach 1:
The patent changes the fundamental operating parameters by using a transistor with extremely low leakage current (1×10^-21 A or less) instead of conventional transistors, enabling data retention without high voltage charge injection. This parameter change allows achieving non-volatile storage characteristics with unlimited write cycles by avoiding gate insulating film deterioration.
Solution Approach 2:
The patent replaces the high voltage charge injection mechanism of FGNVM with a low voltage transistor switching mechanism. By substituting the charge storage mechanism with a leakage-free transistor off-state, the system achieves non-volatile storage without the mechanical stress and film deterioration caused by high voltage operations.
2Duration of action of stationary object
If FGNVM is used to achieve non-volatile storage, then data retention is improved, but integration density deteriorates due to interference between adjacent memory cells requiring larger cell area
Solution Approach 1:
The patent changes the retention mechanism from high voltage charge storage in floating gates to low leakage current transistor switching. This parameter change reduces the memory cell area by eliminating the need for large floating gate structures and reducing interference effects, achieving both non-volatile storage and high integration density.
3Area of stationary object
If DRAM structure is used to achieve high integration density, then area per memory cell is reduced (8 F^2), but data retention deteriorates (data lost within several tens of seconds requiring frequent refresh)
Solution Approach 1:
The patent changes the retention mechanism from capacitor charge storage (DRAM) to transistor leakage current suppression. By using a transistor with leakage current of 1×10^-21 A or less, the system achieves both high integration density (small cell area) and long data retention (one hour or longer) without frequent refresh operations.
4Speed
If SRAM structure is used to achieve fast data access, then data retention is improved during power supply, but integration density deteriorates (100 F^2 per memory cell) and data is lost when power is not supplied
Solution Approach 1:
The patent changes the retention mechanism from active power supply dependence (SRAM) to passive leakage suppression. By using a transistor with extremely low leakage current, the system achieves non-volatile storage with fast access speeds and small cell area, eliminating the need for continuous power supply while maintaining data integrity.
5Ease of manufacture
If conventional memory structures are used, then manufacturing is simplified, but power consumption increases due to frequent refresh operations or high voltage requirements
Solution Approach 1:
The patent changes the operating parameters to use low voltage (avoiding high voltage charge injection) and eliminates frequent refresh operations (by using leakage-free transistor). This parameter change reduces power consumption while maintaining manufacturing simplicity through conventional transistor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables data retention for one hour or longer, supports one million or more write cycles, and achieves an integration density of 40 F^2 or less, reducing power consumption and eliminating the need for high voltage writing, thus overcoming the limitations of existing technologies.
Implementation Method 1
even when a transistor used for switching is in an off state, a slight amount of leakage current is generated between a source and a drain
Implementation Method 2
data is stored by holding charge in a capacitor which is provided in a memory cell
Implementation Method 3
a so-called floating gate is provided between a channel and a gate and charge is stored in the floating gate, whereby data is held
Data Source
AI summary
A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column.