Flash Memory Read Retry Voltage Optimization
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Solution Overview
Problem
Flash memory devices face challenges in maintaining data read speed and reliability due to cell distribution migration and broadening over time, leading to failed read operations, especially in multi-level cell devices with smaller read margins.
Innovation Solution
A method and device that perform iterative read retry operations with increasing voltage levels to successfully read data, starting from a minimum retry voltage identified during a test read operation, and adjusting the sequence of read retry operations based on cell distribution conditions to extend the operational time of the flash memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory devices use multi-level cells to increase storage capacity, then storage density is improved, but read reliability deteriorates due to smaller read margins and cell distribution migration
Solution Approach 1:
The patent performs preliminary characterization of cell distribution at manufacturing time to determine optimal read voltages before the device is deployed. This preliminary action establishes a baseline voltage sequence that accounts for expected cell distribution migration over time, allowing the device to maintain read reliability throughout its operational lifetime despite the reduced margins inherent in multi-level cell designs
Solution Approach 2:
The patent implements dynamic adjustment of read voltage parameters based on detected cell distribution characteristics. By monitoring read failures and adjusting voltage levels in the read sequence, the system adapts to cell distribution migration and broadening effects, maintaining reliable data retrieval from multi-level cells despite deteriorating conditions over time
2Reliability
If flash memory devices perform multiple read retry operations to handle cell distribution migration, then read reliability is improved, but data read speed deteriorates
Solution Approach 1:
The patent pre-determines an optimal sequence of read voltages during manufacturing based on expected cell distribution characteristics. This preliminary voltage sequence is stored in the device and used during normal operation to minimize the number of retry operations needed, thereby maintaining fast read speeds while ensuring reliability even as cell distribution migrates over time
Solution Approach 2:
By using pre-characterized voltage sequences that anticipate cell distribution migration, the patent enables the read operation to skip through potential failure points more efficiently. The optimized voltage sequence allows the system to quickly traverse through necessary voltage levels to successfully read data, reducing the time spent on multiple retry attempts
3Reliability
If flash memory devices use higher read voltages to compensate for cell distribution broadening, then read reliability is improved, but the risk of read disturb increases
Solution Approach 1:
The patent applies different voltage levels from the read sequence to different pages or blocks of memory based on their specific cell distribution characteristics. By characterizing and treating different regions with locally optimized voltages, the system achieves reliable reads in each region without unnecessarily applying high voltages that could cause read disturb in other regions
Solution Approach 2:
The patent dynamically adjusts read voltage parameters based on detected cell distribution characteristics rather than using fixed high voltages. By changing voltage parameters adaptively according to actual cell conditions, the system achieves the minimum necessary voltage to successfully read data, improving reliability while minimizing read disturb effects that would occur with consistently high voltage application
Data Source
AI summary
A flash memory device and method of reading data are disclosed. The method includes; performing a test read operation directed to test data stored in a memory cell array of the flash memory device by iteratively applying a sequence of test read retry operations, wherein each successive test read retry operation uses a respectively higher test read voltage level than a preceding test read retry operation, until one test read retry operation in the sequence of test read retry operations successfully reads the test data using a minimum test read retry voltage associated with the one test read retry operation, setting an initial read voltage for the flash memory device equal to the minimum test read retry voltage, and thereafter performing a normal read operation directed to user data stored in the memory cell array by iteratively applying a sequence of read retry operations, wherein an initial read retry operation in the sequence of read retry operations uses the initial read voltage.