Non-Volatile Memory Read Voltage Determination via Least Erased and Programmed Levels

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Solution Overview

Problem

Selecting optimal read, program verify, and erase verify voltages for non-volatile memory (NVM) cells is challenging due to variations in process conditions, aging, and cycling, leading to increased development time and costs, as the difference between the least erased and least programmed levels may not be large and can shift over time.

Innovation Solution

Determining the least programmed and least erased levels for NVM cells, calculating an operating window, and setting an optimum read reference voltage between these levels, which can be stored and used for normal operation, thereby optimizing the read voltage and reducing the need for extensive characterization and testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If extensive characterization and testing of large numbers of NVM arrays from multiple wafers is performed to determine optimal read voltage, then the accuracy and reliability of read voltage selection is improved, but the development time and cost increase significantly

Engineering Contradiction:
Improveread voltage selection accuracyVSAvoiddevelopment time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent extracts only the critical information needed (least erased level and least programmed level) from a small sample of memory cells, rather than characterizing entire populations. This selective extraction of key parameters enables accurate read voltage determination without extensive testing of all arrays.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary determination of the least erased and least programmed levels on a small subset of cells before final read voltage selection. This preliminary characterization provides sufficient information to establish accurate read voltage without requiring comprehensive testing of all memory arrays.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the difference between LEL and LPL is small, then the memory device can be manufactured with tighter process control, but the selectable window for read voltage becomes constrained by sense amplifier resolution

Engineering Contradiction:
Improveprocess controlVSAvoidsense amplifier resolution requirements
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent determines actual LEL and LPL values through measurement and uses these measured parameters to set the read voltage, rather than relying on fixed design margins. This parameter-based approach adapts to the actual distribution characteristics, allowing accurate read operations even when the voltage window is small.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If LEL and LPL are determined a priori through extensive testing, then optimal read voltage can be selected, but the process cannot account for shifts that occur during the NVM lifetime

Engineering Contradiction:
Improveread voltage optimizationVSAvoidlifetime performance adaptation
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent performs preliminary determination of LEL and LPL levels that can be stored and used for normal operation. These preliminary measurements capture the essential characteristics needed for accurate reading, and the approach can be repeated at different stages to account for aging and drift.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent establishes a method where LEL and LPL levels are determined and can be used to adjust read voltage settings. This creates a feedback mechanism where actual measured levels inform the read operation, allowing the system to adapt to changes in the memory characteristics over time.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8310877B2Read conditions for a non-volatile memory (NVM)
Publication Date: 2012.11.13 NXP USA INC
  • US8310877B2 patent drawing
  • US8310877B2 patent drawing
  • US8310877B2 patent drawing

AI summary

A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level.