NAND Memory Strings Selectively Coupled to Bit Lines
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Solution Overview
Problem
Existing NAND flash memory architectures face limitations in increasing performance, memory density, and reducing power consumption as they rely on traditional read operations that consume significant power and require complex source connections, making it difficult to achieve high memory densities and efficient read operations.
Innovation Solution
The proposed solution involves a modified NAND architecture where adjacent bit lines cross over in an alternating pattern, eliminating the need for a source connection by selectively coupling the ends of NAND strings to different bit lines, allowing for reading using charge sharing techniques or bit lines as virtual grounds, which reduces power consumption and simplifies fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional NAND flash memory architecture with source connection is used, then memory cells can be read using conventional methods, but power consumption increases and device complexity increases
Solution Approach 1:
The patent removes the source connection from the traditional NAND flash memory architecture. By extracting this component, the invention eliminates the need for DC current during read operations, thereby reducing power consumption and simplifying the device structure while maintaining read functionality through alternative bit line coupling methods
Solution Approach 2:
The bit lines in the patent serve multiple functions: they act as both data transmission lines and as replacement for the source connection during read operations. This multi-functionality allows the system to eliminate dedicated source connections while maintaining operational capability, reducing overall device complexity
2Productivity
If traditional read operations are used, then memory data can be read, but power consumption is significant and fabrication complexity increases
Solution Approach 1:
By removing the source connection from the memory cell structure, the patent simplifies the fabrication process and reduces manufacturing complexity. The alternative bit line coupling method achieves read operations without requiring the complex source connection infrastructure, thereby improving ease of manufacture
Solution Approach 2:
The patent changes the electrical parameters and connection methodology of read operations. Instead of using conventional DC current through source connections, the invention employs alternative voltage configurations and bit line coupling methods, which simplifies fabrication while maintaining or improving read operation speed
3Quantity of substance
If higher memory density is achieved, then storage capacity increases, but performance improvements become more difficult to achieve
Solution Approach 1:
By extracting the source connection from the memory cell architecture, the patent enables higher memory density configurations without sacrificing performance. The simplified architecture with bit line coupling allows for more cells per string while maintaining read operation speed through reduced parasitic effects and simpler current paths
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased memory densities, reduced fabrication steps, and faster read operations compared to traditional NAND architectures, with power savings and improved performance due to the elimination of DC current during read operations and simplified processing.
Implementation Method 1
allowing for reading using charge sharing techniques or bit lines as virtual grounds
Data Source
AI summary
Memory devices where ends of series-coupled strings of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device or by using one bit line as a ground node for sensing current flow through the strings. The use of bit lines for virtual grounding is further suitable to other array architectures.