Bit Line Spacer Offset for Memory Cell TPD Reduction
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Solution Overview
Problem
As semiconductor memory devices shrink in size, they face challenges with short channel behavior, reduced drain-source break down voltage (BVdss), and increased column leakage current due to hot electrons disturbing adjacent memory cells, leading to transport program disturb (TPD) issues.
Innovation Solution
The solution involves forming spacers on a semiconductor substrate to constrain bit line implants, increasing the effective channel length and allowing higher energy bit line implants, which form deeper junctions to block hot electrons and prevent TPD, while maintaining scalability and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are scaled down to achieve high density, then circuit density is improved, but hot electrons disturb adjacent memory cells causing TPD
Solution Approach 1:
The patent extends the bit line junction depth into the vertical dimension to block hot electron transport. By forming deeper bit line implants that extend below the channel region, the patent creates a three-dimensional barrier structure that prevents hot electrons generated during programming from reaching adjacent memory cells, thus resolving the TPD issue while maintaining scaled dimensions.
Solution Approach 2:
The patent introduces an intermediate blocked region between the channel and adjacent memory cells. This blocked region, formed by extended bit line junctions, acts as a mediator that intercepts and blocks hot electrons before they can disturb adjacent cells, effectively decoupling the programming process from the harmful hot electron effects.
2Object-affected harmful factors
If bit line implant energy is increased to form deeper junctions, then TPD is prevented, but device short channel roll off issues occur
Solution Approach 1:
The patent applies different implant energies and depths to different regions: high energy implants are used locally at the bit line edges to create deep blocking junctions, while the central channel region maintains lower energy implants to preserve short channel characteristics. This localized differentiation allows deep junctions for TPD prevention without sacrificing device reliability.
Solution Approach 2:
The bit line implant structure is segmented into multiple regions with different depths and doping concentrations. The patent creates shallower implants in the channel region and deeper implants in the blocking region, allowing each segment to optimize its function - the shallow segment maintains device reliability while the deep segment prevents TPD.
3Object-affected harmful factors
If effective channel length is increased to prevent hot electron transport, then TPD is reduced, but device area increases
Solution Approach 1:
Instead of increasing the lateral channel length, the patent blocks hot electron transport by extending bit line junctions into the vertical dimension. This approach creates a blocking barrier that stops hot electron transport without requiring additional lateral space, thus preventing TPD while maintaining compact device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the effective channel length, improves TPD characteristics, and increases drain-source break down voltage (BVdss), thereby improving the programming efficiency and reducing leakage current in memory devices.
Implementation Method 1
The bit line can be formed by an implant process using the spacers in the bit line opening as an implant screen. The spacer can be used to offset the implants.
Implementation Method 2
The spacer can constrain the implant in a narrower implant region, thereby increasing an effective channel length of the memory cell.
Implementation Method 3
Higher energy bit line implant can form deeper bit line junction and can effectively block hot electron move to the adjacent memory cell and prevent TPD.
Data Source
AI summary
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.