Bit Line Voltage Modulation for Nonvolatile Memory Sensing
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Solution Overview
Problem
In flash memory systems, memory cells connected to initially programmed word lines conduct excessive current during verify operations, leading to power wastage, and adjusting bit line voltages during read operations can result in an apparent decrease in threshold voltage, affecting data accuracy.
Innovation Solution
Adjusting the read bit line voltage, verify compare voltage, and/or read compare voltage to compensate for the apparent decrease in threshold voltage, and dividing word lines into zones to apply different bit line voltages during verify operations to reduce excessive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a compare voltage is applied to memory cells connected to initially programmed word lines during verify operations, then the programming level can be verified, but excessive current is conducted leading to power wastage
Solution Approach 1:
The patent applies different bit line voltages to different zones of word lines based on their programming state. Specifically, memory cells connected to initially programmed word lines receive a first bit line voltage, while memory cells connected to unprogrammed word lines receive a second bit line voltage. This localized differentiation reduces excessive current conduction in already-programmed cells during verify operations, thereby reducing power consumption while maintaining verification accuracy.
2Loss of energy
If bit line voltage is adjusted during read operations to reduce current, then power consumption decreases, but the threshold voltage appears to decrease affecting data accuracy
Solution Approach 1:
The patent compensates for the apparent threshold voltage decrease caused by adjusted bit line voltages by modifying the read compare voltage. When a first bit line voltage is applied to reduce current, a corresponding first read compare voltage is used; when a second bit line voltage is applied, a corresponding second read compare voltage is used. This parameter adjustment maintains the relationship between bit line voltage and compare voltage, ensuring accurate data reading while reducing power consumption.
3Device complexity
If the same bit line voltage is applied to all word lines during verify operations, then the circuit design is simple, but memory cells connected to initially programmed word lines conduct excessive current
Solution Approach 1:
The patent divides word lines into different zones based on their programming state and applies different bit line voltages to each zone. Memory cells connected to initially programmed word lines are assigned a first bit line voltage, while memory cells connected to unprogrammed word lines are assigned a second bit line voltage. This segmentation approach manages power consumption effectively while maintaining reasonable circuit design complexity through systematic voltage assignment.
Data Source
AI summary
In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.