Bit Processing Apparatus Using Counter and Bit-Shift Circuitry
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Solution Overview
Problem
Existing bit processing systems require complex and inflexible control circuitry to perform bit-level permutation operations, which are dedicated to specific permutation operations and lack adaptability.
Innovation Solution
The implementation of counter and bit-shift circuitry in a series of processing stages, where each stage operates on contiguous n-bit groups, with n doubling in each subsequent stage, to generate count values and shift data bits based on mask values, allowing for flexible bit permutation operations like BEXT, BGRP, and BDEP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated control circuitry is used for specific permutation operations, then the operation can be performed with precise control, but the device complexity increases and flexibility is reduced
Solution Approach 1:
The patent implements a universal bit processing apparatus that can perform multiple permutation operations (BEXT, BGRP, BDEP) using the same hardware circuitry. The counter circuitry and bit-shift circuitry work together in a coordinated manner to achieve different permutation functions by varying the control signals, eliminating the need for separate dedicated circuits for each operation type.
Solution Approach 2:
The apparatus uses dynamic control signals to reconfigure the behavior of the counter and bit-shift circuitry based on the desired permutation operation. The control circuitry dynamically adjusts the counting behavior and shift amounts to perform different operations, making the system adaptable rather than static and dedicated to a single function.
2Reliability
If dedicated control circuitry is used for specific permutation operations, then the operation can be performed with precise control, but the adaptability decreases
Solution Approach 1:
The same counter circuitry and bit-shift circuitry are used to perform multiple permutation operations (BEXT, BGRP, BDEP). The universal design allows the apparatus to adapt to different operation types by receiving different control signals, while maintaining precise control through the coordinated interaction of the circuit components.
Solution Approach 2:
The control circuitry dynamically reconfigures the counter and bit-shift operations based on which permutation operation is required. By varying control signals, the system can switch between different permutation modes, providing high adaptability without sacrificing control precision.
3Productivity
If n-bit groups processing is used with doubling n in each stage, then the bit processing efficiency is improved, but the number of processing stages increases
Solution Approach 1:
The bit processing is divided into multiple stages, where each stage processes n-bit groups of bits. The value of n doubles in each subsequent stage (1, 2, 4, 8, ...), creating a segmented processing approach that handles increasing numbers of bits per stage. This segmentation allows efficient parallel processing within each stage while managing overall complexity.
Solution Approach 2:
The processing stages are nested in a hierarchical structure where each stage builds upon the previous one. The n-bit groups processed in earlier stages are combined and reprocessed in later stages with larger n values, creating a nested processing pattern that efficiently handles the entire bit sequence through progressive aggregation.
Data Source
AI summary
Apparatus comprises counter and bit-shift circuitry to provide a succession of processing stages each comprising a count operation stage and a corresponding bit-shift stage, each processing stage operating with respect to a set of contiguous n-bit groups of bit positions, where n is 1 for a first processing stage and n doubles from one processing stage in the succession of processing stages to a next processing stage in the succession of processing stages; each count operation stage being configured to generate, for a first set of alternate instances of the n-bit groups of bit positions, count values indicating a respective number of bits of a predetermined bit value in a mask data word; and each bit-shift stage being configured to generate a bit-shifted data word by bit-shifting bits of a data word to be processed, for a second set of alternate instances of the n-bit groups of bit positions complementary to the first set, by respective numbers of bit positions dependent upon the count values generated by the respective count operation stage, in which the bit-shifted data word for one bit-shift stage in the succession of processing stages is used as the data word to be processed by the next bit-shift stage in the succession of processing stages.