Bit-Serial Linear Algebra Processor with Variable Precision

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Solution Overview

Problem

Current computing systems are inefficient in performing linear algebraic operations, particularly matrix-matrix multiplications, which are fundamental in science and engineering, due to limitations in precision and processing speed.

Innovation Solution

A computing system with a co-processing module comprising a parallel array of bit-serial processing units that perform linear algebraic operations with variable precision, utilizing a data reorganization unit to transform data from byte-wise to bit-serial format and a data supply unit to manage bit-width configuration for efficient processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional computing systems are used for linear algebraic operations, then processing speed is limited, but power consumption and data movement are increased

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The computing system is segmented into multiple bit-serial processing units arranged in a parallel array, where each unit processes individual bits of data. This segmentation enables high-speed parallel processing of linear algebraic operations while reducing the power consumption of each individual unit compared to conventional full-precision processors.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If conventional computing systems perform linear algebraic operations with fixed precision, then processing speed is limited, but flexibility in data type support is reduced

Engineering Contradiction:

Improveflexibility in data type supportVSAvoidprocessing speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The bit-serial processing units dynamically adjust their precision settings to match the requirements of different data types and operations. Each processing unit can be configured to process data at different bit widths, enabling flexible support for various precision requirements (e.g., 8-bit, 16-bit, 32-bit) while maintaining high processing speed through the bit-serial architecture.

Inventive Principle:

Principle #15Dynamics

3Productivity

If data is processed in byte-wise format, then memory layout is simplified, but data movement and processing efficiency are increased

Engineering Contradiction:

Improveprocessing efficiencyVSAvoiddata movement

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The system transforms data from traditional byte-wise processing to bit-serial processing, effectively changing the dimension of data representation. Data is reorganized into a bit-serial format where bits are processed sequentially through the parallel array of processing units, reducing the amount of data movement required and improving processing efficiency for linear algebraic operations.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11275713B2Bit-serial linear algebra processor

Publication Date: 2022.03.15 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

The invention is notably directed to a computing system configured to perform linear algebraic operations. The computing system comprises a co-processing module comprising a co-processing unit. The co-processing unit comprises a parallel array of bit-serial processing units. The bit-serial processing units are adapted to perform the linear algebraic operations with variable precision. The invention further concerns a related computer implemented method and a related computer program product.