Systolic Arrays TRIZ Cases
- Embedded Programmable Logic for Deep Learning Processor Adaptability
Embedding programmable logic devices within deep learning processors provides flexible reconfigurable support functions.
- Reconfigurable Processing Element for Systolic Array Matrix Multiplication
A reconfigurable processing element uses multiplexer circuitry to switch between weight stationary and output stationary modes in a systolic array.
- MxN Systolic Array Mode Switching for Processing Element Utilization
Dynamic mode switching between row-major and column-major configurations maximizes processing element utilization in MxN systolic arrays.
- Sequential Memory Architecture for High-Speed Data Stream Processing
A computing architecture with sequential memory locations processes data streams using dedicated processing elements.
- Systolic Array Data Reuse for Memory Bandwidth Reduction
A systolic array structure processes data reuse schemes across two dimensions to accelerate computation.