Reconfigurable Processing Element for Systolic Array Matrix Multiplication
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Solution Overview
Problem
Existing systolic arrays for matrix multiplication are limited as they can only operate in either output stationary mode or weight stationary mode, which may not be efficient for all matrix dimensions and architectures.
Innovation Solution
A reconfigurable processing element for a systolic array that is configurable for multiplying a first matrix with a second matrix to determine a result matrix in either a weight stationary mode or an output stationary mode, utilizing first and second input ports, multiplexer circuitry, an internal register, a multiplier circuit, and an adder circuit, with control signals determining the operational mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a systolic array is designed to operate in a fixed mode (either weight stationary or output stationary), then the architecture is simpler and easier to implement, but it cannot efficiently handle all matrix dimensions and computation patterns
Solution Approach 1:
The processing element is designed with universal functionality to support both weight stationary and output stationary modes through reconfigurable multiplexer circuitry. The same hardware structure can perform different computation patterns by changing the configuration of multiplexers, eliminating the need for separate dedicated hardware for each mode and achieving multi-functionality from a single processing element design
Solution Approach 2:
The processing element incorporates dynamic reconfiguration capability through control signals that change the operational mode based on computation requirements. The multiplexer circuitry can be dynamically switched between different configurations during operation, allowing the system to adapt to varying matrix dimensions and computation patterns without physical reconfiguration of the hardware architecture
2Productivity
If the systolic array uses reconfigurable processing elements with multiplexer circuitry to support both weight stationary and output stationary modes, then computational efficiency is improved for various matrix dimensions, but the device complexity and area increase
Solution Approach 1:
The design merges the functionality of separate weight stationary and output stationary processing elements into a single unified processing element. By combining the computational units, multiplexer circuitry, and control logic into one integrated structure, the patent achieves both computation modes within a compact area, avoiding the need to duplicate entire processing element sets for each mode
Solution Approach 2:
The processing element achieves multi-functionality by incorporating reconfigurable multiplexer circuitry that can route data differently based on the operational mode. This universal design allows the same hardware resources to serve multiple computation patterns, improving productivity without proportionally increasing the area, as the additional complexity is confined to control logic rather than duplicating entire computational paths
Data Source
AI summary
A reconfigurable processing element for a systolic array that is configurable for multiplying a first matrix with a second matrix to determine a result matrix in a weight stationary mode or in an output stationary mode is presented. Furthermore, a systolic array for performing matrix multiplication of a first matrix and a second matrix to determine a result matrix is presented that includes a plurality of reconfigurable processing elements that are configurable for operating in a weight stationary mode or in an output stationary mode. Moreover, a method of operating a reconfigurable processing element for a systolic array that is configured for performing matrix multiplication of a first matrix and a second matrix to determine a result matrix in a weight stationary mode or in an output stationary mode is presented.