Embedded Programmable Logic for Deep Learning Processor Adaptability
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Solution Overview
Problem
Deep learning-focused processors, such as ASICs and GPUs, face sub-optimal utilization due to bottlenecks in support functions that evolve faster than their design and production, leading to inefficiencies in systolic compute units and a lack of flexibility to accommodate new support functions over time.
Innovation Solution
Embedding programmable logic devices, like FPGAs, within or near these processors to provide flexible and reconfigurable logic that can adapt to evolving network demands, optimizing systolic arrays and near-memory computes for improved efficiency and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ASICs and GPUs with fixed architecture are used for deep learning processing, then initial performance is achieved, but they cannot adapt to evolving network demands and support functions
Solution Approach 1:
The patent applies dynamics by making the support functions reconfigurable through embedded programmable logic devices. The fixed architecture is transformed into a dynamic system where support functions can be programmed and reprogrammed to match evolving deep learning network requirements, resolving the contradiction between initial performance and future adaptability.
Solution Approach 2:
The patent implements universality by designing support functions that can perform multiple different operations through programmable logic. Instead of dedicated hardware for each support function, a single reconfigurable unit can be programmed to handle various support tasks, enabling the system to adapt to different network architectures and requirements over time.
2Adaptability or versatility
If dedicated support processors are added to ASICs, then initial support functions are handled, but new support functions cannot be accommodated without new hardware designs
Solution Approach 1:
The patent transforms static support processors into dynamic, reconfigurable units by embedding programmable logic devices. This allows the support function architecture to evolve through software updates rather than requiring complex hardware redesigns, reducing device complexity while maintaining flexibility.
Solution Approach 2:
The patent changes the fundamental parameter of support function implementation from fixed hardware configuration to programmable logic configuration. By altering how support functions are realized (from dedicated circuits to programmable devices), the system gains flexibility without proportionally increasing hardware complexity.
3Productivity
If fixed-function support processors are used, then current deep learning networks are supported, but bottlenecks occur when networks evolve faster than ASIC production
Solution Approach 1:
The patent resolves the time lag by making support functions dynamically reconfigurable. Instead of waiting for lengthy ASIC production cycles to update support functions, the system can be reprogrammed in field, allowing near-real-time adaptation to evolving deep learning networks and maintaining high systolic compute unit utilization.
Solution Approach 2:
The patent applies preliminary action by pre-embedding programmable logic capability in the ASIC design, enabling future support functions to be programmed in advance or updated quickly without requiring new hardware production cycles. This preliminary inclusion of reconfigurability eliminates the time lag between network evolution and ASIC updates.
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AI summary
Processors may be enhanced by embedding programmable logic devices, such as field-programmable gate arrays. For instance, an application-specific integrated circuit device may include main fixed function circuitry operable to perform a main fixed function of the application-specific integrated circuit device. The application-specific integrated circuit also includes a support processor that performs operations outside of the main fixed function of the application-specific integrated circuit device, wherein the support processor comprises an embedded programmable fabric to provide programmable flexibility to application-specific integrated circuit device.