Sequential Memory Architecture for High-Speed Data Stream Processing
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Solution Overview
Problem
Existing computer architectures are not optimized to process generalized streams of data efficiently, as they typically require sequential logic to be reapplied to new data after processing, leading to inefficiencies in handling arbitrary data streams.
Innovation Solution
A computer architecture with sequential memory locations connected by both a data bus and a signal bus, where data and metadata are operated on in a serial, temporal fashion, allowing each datum in a data stream to experience the same algorithm with minimal latency and no impact on bandwidth, enabling high-speed processing of arbitrary computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional computer architectures (Princeton or Harvard) are used to process data streams, then data can be stored and processed using standard memory and bus structures, but processing speed is significantly limited due to sequential logic requirements and repeated application of algorithms to new data
Solution Approach 1:
The memory is segmented into a sequence of processing elements, each responsible for a specific computational step. This segmentation allows the data stream to be processed in parallel across multiple memory locations simultaneously, eliminating the sequential bottleneck of traditional architectures while maintaining manageable complexity through modular processing units.
Solution Approach 2:
The patent transitions from traditional temporal processing (processing data sequentially in time) to spatial-temporal processing by arranging processing elements in a spatial sequence within memory. This dimensional change enables simultaneous processing of multiple data elements at different stages of computation, dramatically increasing throughput without requiring complex external processing hardware.
2Productivity
If sequential logic is reapplied to new data after processing in traditional architectures, then algorithmic flexibility is maintained, but processing efficiency decreases due to repeated operations and latency
Solution Approach 1:
The processing elements are pre-configured in sequence within memory, with each element prepared to perform its specific computational operation. This preliminary arrangement eliminates the need to repeatedly apply sequential logic during data processing, as the algorithmic steps are already in place and can be executed in parallel as data flows through the memory sequence, reducing latency and improving efficiency.
3Use of energy by moving object
If a centralized CPU processes data in traditional architectures, then programming simplicity is maintained, but power consumption increases due to continuous data transfer and processing operations
Solution Approach 1:
The processing elements within memory are self-contained and autonomously execute their designated operations on passing data without requiring continuous intervention from a centralized CPU. Each processing element manages its own computational task, reducing the overall power consumption by eliminating the need for constant data transfer and control signals to a central processor, while maintaining programming simplicity through the sequential memory structure.
Data Source
AI summary
A data stream processing unit (DPU) and method for use are provided. A DPU includes a number of processing elements arranged in a sequence, and each datum in the data stream visits each processing element in sequence. Each processing element has a memory circuit, data and metadata input and output channels, and a computing circuit. The metadata input represents a partial computational state that is associated with each datum as it passes through the DPU. The computing circuit for each processing element operates on the data and metadata inputs as a function of its position in the sequence, producing an altered partial computational state that accompanies the datum. Each computing circuit may be modeled, for example, as a finite state machine, and the collection of processing elements cooperate to perform the computation. The computing circuits may be collectively programmed to perform any desired computation.